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    <h1>File: /Users/paulross/dev/linux/linux-3.13/arch/x86/include/uapi/asm/msr-index.h</h1>
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    <pre><a name="1" /><span class="True">       1:</span> <span class="f">#</span><span class="n">ifndef</span> <a href="cpu.c_macros_noref.html#_X0FTTV9YODZfTVNSX0lOREVYX0hfMA__"><span class="b">_ASM_X86_MSR_INDEX_H</span></a>
<a name="2" /><span class="True">       2:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_X0FTTV9YODZfTVNSX0lOREVYX0hfMA__"><span class="b">_ASM_X86_MSR_INDEX_H</span></a>
<a name="3" /><span class="True">       3:</span> 
<a name="4" /><span class="True">       4:</span> <span class="k">/* CPU model specific register (MSR) numbers */</span>
<a name="5" /><span class="True">       5:</span> 
<a name="6" /><span class="True">       6:</span> <span class="k">/* x86-64 specific MSRs */</span>
<a name="7" /><span class="True">       7:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0VGRVJfMA__"><span class="b">MSR_EFER</span></a>        <span class="c">0xc0000080</span> <span class="k">/* extended feature register */</span>
<a name="8" /><span class="True">       8:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1NUQVJfMA__"><span class="b">MSR_STAR</span></a>        <span class="c">0xc0000081</span> <span class="k">/* legacy mode SYSCALL target */</span>
<a name="9" /><span class="True">       9:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0xTVEFSXzA_"><span class="b">MSR_LSTAR</span></a>        <span class="c">0xc0000082</span> <span class="k">/* long mode SYSCALL target */</span>
<a name="10" /><span class="True">      10:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0NTVEFSXzA_"><span class="b">MSR_CSTAR</span></a>        <span class="c">0xc0000083</span> <span class="k">/* compat mode SYSCALL target */</span>
<a name="11" /><span class="True">      11:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1NZU0NBTExfTUFTS18w"><span class="b">MSR_SYSCALL_MASK</span></a>    <span class="c">0xc0000084</span> <span class="k">/* EFLAGS mask for syscall */</span>
<a name="12" /><span class="True">      12:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0ZTX0JBU0VfMA__"><span class="b">MSR_FS_BASE</span></a>        <span class="c">0xc0000100</span> <span class="k">/* 64bit FS base */</span>
<a name="13" /><span class="True">      13:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0dTX0JBU0VfMA__"><span class="b">MSR_GS_BASE</span></a>        <span class="c">0xc0000101</span> <span class="k">/* 64bit GS base */</span>
<a name="14" /><span class="True">      14:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0tFUk5FTF9HU19CQVNFXzA_"><span class="b">MSR_KERNEL_GS_BASE</span></a>    <span class="c">0xc0000102</span> <span class="k">/* SwapGS GS shadow */</span>
<a name="15" /><span class="True">      15:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1RTQ19BVVhfMA__"><span class="b">MSR_TSC_AUX</span></a>        <span class="c">0xc0000103</span> <span class="k">/* Auxiliary TSC */</span>
<a name="16" /><span class="True">      16:</span> 
<a name="17" /><span class="True">      17:</span> <span class="k">/* EFER bits: */</span>
<a name="18" /><span class="True">      18:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_X0VGRVJfU0NFXzA_"><span class="b">_EFER_SCE</span></a>        <span class="c">0</span>  <span class="k">/* SYSCALL/SYSRET */</span>
<a name="19" /><span class="True">      19:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_X0VGRVJfTE1FXzA_"><span class="b">_EFER_LME</span></a>        <span class="c">8</span>  <span class="k">/* Long mode enable */</span>
<a name="20" /><span class="True">      20:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_X0VGRVJfTE1BXzA_"><span class="b">_EFER_LMA</span></a>        <span class="c">10</span> <span class="k">/* Long mode active (read-only) */</span>
<a name="21" /><span class="True">      21:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_X0VGRVJfTlhfMA__"><span class="b">_EFER_NX</span></a>        <span class="c">11</span> <span class="k">/* No execute enable */</span>
<a name="22" /><span class="True">      22:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_X0VGRVJfU1ZNRV8w"><span class="b">_EFER_SVME</span></a>        <span class="c">12</span> <span class="k">/* Enable virtualization */</span>
<a name="23" /><span class="True">      23:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_X0VGRVJfTE1TTEVfMA__"><span class="b">_EFER_LMSLE</span></a>        <span class="c">13</span> <span class="k">/* Long Mode Segment Limit Enable */</span>
<a name="24" /><span class="True">      24:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_X0VGRVJfRkZYU1JfMA__"><span class="b">_EFER_FFXSR</span></a>        <span class="c">14</span> <span class="k">/* Enable Fast FXSAVE/FXRSTOR */</span>
<a name="25" /><span class="True">      25:</span> 
<a name="26" /><span class="True">      26:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_RUZFUl9TQ0VfMA__"><span class="b">EFER_SCE</span></a>        <span class="f">(</span><span class="c">1</span><span class="f">&lt;&lt;</span><a href="cpu.c_macros_noref.html#_X0VGRVJfU0NFXzA_"><span class="b">_EFER_SCE</span></a><span class="f">)</span>
<a name="27" /><span class="True">      27:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_RUZFUl9MTUVfMA__"><span class="b">EFER_LME</span></a>        <span class="f">(</span><span class="c">1</span><span class="f">&lt;&lt;</span><a href="cpu.c_macros_noref.html#_X0VGRVJfTE1FXzA_"><span class="b">_EFER_LME</span></a><span class="f">)</span>
<a name="28" /><span class="True">      28:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_RUZFUl9MTUFfMA__"><span class="b">EFER_LMA</span></a>        <span class="f">(</span><span class="c">1</span><span class="f">&lt;&lt;</span><a href="cpu.c_macros_noref.html#_X0VGRVJfTE1BXzA_"><span class="b">_EFER_LMA</span></a><span class="f">)</span>
<a name="29" /><span class="True">      29:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_RUZFUl9OWF8w"><span class="b">EFER_NX</span></a>            <span class="f">(</span><span class="c">1</span><span class="f">&lt;&lt;</span><a href="cpu.c_macros_noref.html#_X0VGRVJfTlhfMA__"><span class="b">_EFER_NX</span></a><span class="f">)</span>
<a name="30" /><span class="True">      30:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_RUZFUl9TVk1FXzA_"><span class="b">EFER_SVME</span></a>        <span class="f">(</span><span class="c">1</span><span class="f">&lt;&lt;</span><a href="cpu.c_macros_noref.html#_X0VGRVJfU1ZNRV8w"><span class="b">_EFER_SVME</span></a><span class="f">)</span>
<a name="31" /><span class="True">      31:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_RUZFUl9MTVNMRV8w"><span class="b">EFER_LMSLE</span></a>        <span class="f">(</span><span class="c">1</span><span class="f">&lt;&lt;</span><a href="cpu.c_macros_noref.html#_X0VGRVJfTE1TTEVfMA__"><span class="b">_EFER_LMSLE</span></a><span class="f">)</span>
<a name="32" /><span class="True">      32:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_RUZFUl9GRlhTUl8w"><span class="b">EFER_FFXSR</span></a>        <span class="f">(</span><span class="c">1</span><span class="f">&lt;&lt;</span><a href="cpu.c_macros_noref.html#_X0VGRVJfRkZYU1JfMA__"><span class="b">_EFER_FFXSR</span></a><span class="f">)</span>
<a name="33" /><span class="True">      33:</span> 
<a name="34" /><span class="True">      34:</span> <span class="k">/* Intel MSRs. Some also available on other CPUs */</span>
<a name="35" /><span class="True">      35:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfUEVSRkNUUjBfMA__"><span class="b">MSR_IA32_PERFCTR0</span></a>        <span class="c">0x000000c1</span>
<a name="36" /><span class="True">      36:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfUEVSRkNUUjFfMA__"><span class="b">MSR_IA32_PERFCTR1</span></a>        <span class="c">0x000000c2</span>
<a name="37" /><span class="True">      37:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0ZTQl9GUkVRXzA_"><span class="b">MSR_FSB_FREQ</span></a>            <span class="c">0x000000cd</span>
<a name="38" /><span class="True">      38:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX05ITV9QTEFURk9STV9JTkZPXzA_"><span class="b">MSR_NHM_PLATFORM_INFO</span></a>        <span class="c">0x000000ce</span>
<a name="39" /><span class="True">      39:</span> 
<a name="40" /><span class="True">      40:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX05ITV9TTkJfUEtHX0NTVF9DRkdfQ1RMXzA_"><span class="b">MSR_NHM_SNB_PKG_CST_CFG_CTL</span></a>    <span class="c">0x000000e2</span>
<a name="41" /><span class="True">      41:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TkhNX0MzX0FVVE9fREVNT1RFXzA_"><span class="b">NHM_C3_AUTO_DEMOTE</span></a>        <span class="f">(</span><span class="c">1UL</span> <span class="f">&lt;&lt;</span> <span class="c">25</span><span class="f">)</span>
<a name="42" /><span class="True">      42:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TkhNX0MxX0FVVE9fREVNT1RFXzA_"><span class="b">NHM_C1_AUTO_DEMOTE</span></a>        <span class="f">(</span><span class="c">1UL</span> <span class="f">&lt;&lt;</span> <span class="c">26</span><span class="f">)</span>
<a name="43" /><span class="True">      43:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_QVRNX0xOQ19DNl9BVVRPX0RFTU9URV8w"><span class="b">ATM_LNC_C6_AUTO_DEMOTE</span></a>        <span class="f">(</span><span class="c">1UL</span> <span class="f">&lt;&lt;</span> <span class="c">25</span><span class="f">)</span>
<a name="44" /><span class="True">      44:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_U05CX0MxX0FVVE9fVU5ERU1PVEVfMA__"><span class="b">SNB_C1_AUTO_UNDEMOTE</span></a>        <span class="f">(</span><span class="c">1UL</span> <span class="f">&lt;&lt;</span> <span class="c">27</span><span class="f">)</span>
<a name="45" /><span class="True">      45:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_U05CX0MzX0FVVE9fVU5ERU1PVEVfMA__"><span class="b">SNB_C3_AUTO_UNDEMOTE</span></a>        <span class="f">(</span><span class="c">1UL</span> <span class="f">&lt;&lt;</span> <span class="c">28</span><span class="f">)</span>
<a name="46" /><span class="True">      46:</span> 
<a name="47" /><span class="True">      47:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1BMQVRGT1JNX0lORk9fMA__"><span class="b">MSR_PLATFORM_INFO</span></a>        <span class="c">0x000000ce</span>
<a name="48" /><span class="True">      48:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX01UUlJjYXBfMA__"><span class="b">MSR_MTRRcap</span></a>            <span class="c">0x000000fe</span>
<a name="49" /><span class="True">      49:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfQkJMX0NSX0NUTF8w"><span class="b">MSR_IA32_BBL_CR_CTL</span></a>        <span class="c">0x00000119</span>
<a name="50" /><span class="True">      50:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfQkJMX0NSX0NUTDNfMA__"><span class="b">MSR_IA32_BBL_CR_CTL3</span></a>        <span class="c">0x0000011e</span>
<a name="51" /><span class="True">      51:</span> 
<a name="52" /><span class="True">      52:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfU1lTRU5URVJfQ1NfMA__"><span class="b">MSR_IA32_SYSENTER_CS</span></a>        <span class="c">0x00000174</span>
<a name="53" /><span class="True">      53:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfU1lTRU5URVJfRVNQXzA_"><span class="b">MSR_IA32_SYSENTER_ESP</span></a>        <span class="c">0x00000175</span>
<a name="54" /><span class="True">      54:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfU1lTRU5URVJfRUlQXzA_"><span class="b">MSR_IA32_SYSENTER_EIP</span></a>        <span class="c">0x00000176</span>
<a name="55" /><span class="True">      55:</span> 
<a name="56" /><span class="True">      56:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUNHX0NBUF8w"><span class="b">MSR_IA32_MCG_CAP</span></a>        <span class="c">0x00000179</span>
<a name="57" /><span class="True">      57:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUNHX1NUQVRVU18w"><span class="b">MSR_IA32_MCG_STATUS</span></a>        <span class="c">0x0000017a</span>
<a name="58" /><span class="True">      58:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUNHX0NUTF8w"><span class="b">MSR_IA32_MCG_CTL</span></a>        <span class="c">0x0000017b</span>
<a name="59" /><span class="True">      59:</span> 
<a name="60" /><span class="True">      60:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX09GRkNPUkVfUlNQXzBfMA__"><span class="b">MSR_OFFCORE_RSP_0</span></a>        <span class="c">0x000001a6</span>
<a name="61" /><span class="True">      61:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX09GRkNPUkVfUlNQXzFfMA__"><span class="b">MSR_OFFCORE_RSP_1</span></a>        <span class="c">0x000001a7</span>
<a name="62" /><span class="True">      62:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX05ITV9UVVJCT19SQVRJT19MSU1JVF8w"><span class="b">MSR_NHM_TURBO_RATIO_LIMIT</span></a>    <span class="c">0x000001ad</span>
<a name="63" /><span class="True">      63:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lWVF9UVVJCT19SQVRJT19MSU1JVF8w"><span class="b">MSR_IVT_TURBO_RATIO_LIMIT</span></a>    <span class="c">0x000001ae</span>
<a name="64" /><span class="True">      64:</span> 
<a name="65" /><span class="True">      65:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0xCUl9TRUxFQ1RfMA__"><span class="b">MSR_LBR_SELECT</span></a>            <span class="c">0x000001c8</span>
<a name="66" /><span class="True">      66:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0xCUl9UT1NfMA__"><span class="b">MSR_LBR_TOS</span></a>            <span class="c">0x000001c9</span>
<a name="67" /><span class="True">      67:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0xCUl9OSE1fRlJPTV8w"><span class="b">MSR_LBR_NHM_FROM</span></a>        <span class="c">0x00000680</span>
<a name="68" /><span class="True">      68:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0xCUl9OSE1fVE9fMA__"><span class="b">MSR_LBR_NHM_TO</span></a>            <span class="c">0x000006c0</span>
<a name="69" /><span class="True">      69:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0xCUl9DT1JFX0ZST01fMA__"><span class="b">MSR_LBR_CORE_FROM</span></a>        <span class="c">0x00000040</span>
<a name="70" /><span class="True">      70:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0xCUl9DT1JFX1RPXzA_"><span class="b">MSR_LBR_CORE_TO</span></a>            <span class="c">0x00000060</span>
<a name="71" /><span class="True">      71:</span> 
<a name="72" /><span class="True">      72:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfUEVCU19FTkFCTEVfMA__"><span class="b">MSR_IA32_PEBS_ENABLE</span></a>        <span class="c">0x000003f1</span>
<a name="73" /><span class="True">      73:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfRFNfQVJFQV8w"><span class="b">MSR_IA32_DS_AREA</span></a>        <span class="c">0x00000600</span>
<a name="74" /><span class="True">      74:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfUEVSRl9DQVBBQklMSVRJRVNfMA__"><span class="b">MSR_IA32_PERF_CAPABILITIES</span></a>    <span class="c">0x00000345</span>
<a name="75" /><span class="True">      75:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1BFQlNfTERfTEFUX1RIUkVTSE9MRF8w"><span class="b">MSR_PEBS_LD_LAT_THRESHOLD</span></a>    <span class="c">0x000003f6</span>
<a name="76" /><span class="True">      76:</span> 
<a name="77" /><span class="True">      77:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX01UUlJmaXg2NEtfMDAwMDBfMA__"><span class="b">MSR_MTRRfix64K_00000</span></a>        <span class="c">0x00000250</span>
<a name="78" /><span class="True">      78:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX01UUlJmaXgxNktfODAwMDBfMA__"><span class="b">MSR_MTRRfix16K_80000</span></a>        <span class="c">0x00000258</span>
<a name="79" /><span class="True">      79:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX01UUlJmaXgxNktfQTAwMDBfMA__"><span class="b">MSR_MTRRfix16K_A0000</span></a>        <span class="c">0x00000259</span>
<a name="80" /><span class="True">      80:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX01UUlJmaXg0S19DMDAwMF8w"><span class="b">MSR_MTRRfix4K_C0000</span></a>        <span class="c">0x00000268</span>
<a name="81" /><span class="True">      81:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX01UUlJmaXg0S19DODAwMF8w"><span class="b">MSR_MTRRfix4K_C8000</span></a>        <span class="c">0x00000269</span>
<a name="82" /><span class="True">      82:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX01UUlJmaXg0S19EMDAwMF8w"><span class="b">MSR_MTRRfix4K_D0000</span></a>        <span class="c">0x0000026a</span>
<a name="83" /><span class="True">      83:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX01UUlJmaXg0S19EODAwMF8w"><span class="b">MSR_MTRRfix4K_D8000</span></a>        <span class="c">0x0000026b</span>
<a name="84" /><span class="True">      84:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX01UUlJmaXg0S19FMDAwMF8w"><span class="b">MSR_MTRRfix4K_E0000</span></a>        <span class="c">0x0000026c</span>
<a name="85" /><span class="True">      85:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX01UUlJmaXg0S19FODAwMF8w"><span class="b">MSR_MTRRfix4K_E8000</span></a>        <span class="c">0x0000026d</span>
<a name="86" /><span class="True">      86:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX01UUlJmaXg0S19GMDAwMF8w"><span class="b">MSR_MTRRfix4K_F0000</span></a>        <span class="c">0x0000026e</span>
<a name="87" /><span class="True">      87:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX01UUlJmaXg0S19GODAwMF8w"><span class="b">MSR_MTRRfix4K_F8000</span></a>        <span class="c">0x0000026f</span>
<a name="88" /><span class="True">      88:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX01UUlJkZWZUeXBlXzA_"><span class="b">MSR_MTRRdefType</span></a>            <span class="c">0x000002ff</span>
<a name="89" /><span class="True">      89:</span> 
<a name="90" /><span class="True">      90:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfQ1JfUEFUXzA_"><span class="b">MSR_IA32_CR_PAT</span></a>            <span class="c">0x00000277</span>
<a name="91" /><span class="True">      91:</span> 
<a name="92" /><span class="True">      92:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_TVNSX0lBMzJfREVCVUdDVExNU1JfMA__"><span class="b">MSR_IA32_DEBUGCTLMSR</span></a>        <span class="c">0x000001d9</span>
<a name="93" /><span class="True">      93:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTEFTVEJSQU5DSEZST01JUF8w"><span class="b">MSR_IA32_LASTBRANCHFROMIP</span></a>    <span class="c">0x000001db</span>
<a name="94" /><span class="True">      94:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTEFTVEJSQU5DSFRPSVBfMA__"><span class="b">MSR_IA32_LASTBRANCHTOIP</span></a>        <span class="c">0x000001dc</span>
<a name="95" /><span class="True">      95:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTEFTVElOVEZST01JUF8w"><span class="b">MSR_IA32_LASTINTFROMIP</span></a>        <span class="c">0x000001dd</span>
<a name="96" /><span class="True">      96:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTEFTVElOVFRPSVBfMA__"><span class="b">MSR_IA32_LASTINTTOIP</span></a>        <span class="c">0x000001de</span>
<a name="97" /><span class="True">      97:</span> 
<a name="98" /><span class="True">      98:</span> <span class="k">/* DEBUGCTLMSR bits (others vary by model): */</span>
<a name="99" /><span class="True">      99:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_REVCVUdDVExNU1JfTEJSXzA_"><span class="b">DEBUGCTLMSR_LBR</span></a>            <span class="f">(</span><span class="c">1UL</span> <span class="f">&lt;&lt;</span>  <span class="c">0</span><span class="f">)</span> <span class="k">/* last branch recording */</span>
<a name="100" /><span class="True">     100:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_REVCVUdDVExNU1JfQlRGXzA_"><span class="b">DEBUGCTLMSR_BTF</span></a>            <span class="f">(</span><span class="c">1UL</span> <span class="f">&lt;&lt;</span>  <span class="c">1</span><span class="f">)</span> <span class="k">/* single-step on branches */</span>
<a name="101" /><span class="True">     101:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_REVCVUdDVExNU1JfVFJfMA__"><span class="b">DEBUGCTLMSR_TR</span></a>            <span class="f">(</span><span class="c">1UL</span> <span class="f">&lt;&lt;</span>  <span class="c">6</span><span class="f">)</span>
<a name="102" /><span class="True">     102:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_REVCVUdDVExNU1JfQlRTXzA_"><span class="b">DEBUGCTLMSR_BTS</span></a>            <span class="f">(</span><span class="c">1UL</span> <span class="f">&lt;&lt;</span>  <span class="c">7</span><span class="f">)</span>
<a name="103" /><span class="True">     103:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_REVCVUdDVExNU1JfQlRJTlRfMA__"><span class="b">DEBUGCTLMSR_BTINT</span></a>        <span class="f">(</span><span class="c">1UL</span> <span class="f">&lt;&lt;</span>  <span class="c">8</span><span class="f">)</span>
<a name="104" /><span class="True">     104:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_REVCVUdDVExNU1JfQlRTX09GRl9PU18w"><span class="b">DEBUGCTLMSR_BTS_OFF_OS</span></a>        <span class="f">(</span><span class="c">1UL</span> <span class="f">&lt;&lt;</span>  <span class="c">9</span><span class="f">)</span>
<a name="105" /><span class="True">     105:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_REVCVUdDVExNU1JfQlRTX09GRl9VU1JfMA__"><span class="b">DEBUGCTLMSR_BTS_OFF_USR</span></a>        <span class="f">(</span><span class="c">1UL</span> <span class="f">&lt;&lt;</span> <span class="c">10</span><span class="f">)</span>
<a name="106" /><span class="True">     106:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_REVCVUdDVExNU1JfRlJFRVpFX0xCUlNfT05fUE1JXzA_"><span class="b">DEBUGCTLMSR_FREEZE_LBRS_ON_PMI</span></a>    <span class="f">(</span><span class="c">1UL</span> <span class="f">&lt;&lt;</span> <span class="c">11</span><span class="f">)</span>
<a name="107" /><span class="True">     107:</span> 
<a name="108" /><span class="True">     108:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfUE9XRVJfQ1RMXzA_"><span class="b">MSR_IA32_POWER_CTL</span></a>        <span class="c">0x000001fc</span>
<a name="109" /><span class="True">     109:</span> 
<a name="110" /><span class="True">     110:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUMwX0NUTF8w"><span class="b">MSR_IA32_MC0_CTL</span></a>        <span class="c">0x00000400</span>
<a name="111" /><span class="True">     111:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUMwX1NUQVRVU18w"><span class="b">MSR_IA32_MC0_STATUS</span></a>        <span class="c">0x00000401</span>
<a name="112" /><span class="True">     112:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUMwX0FERFJfMA__"><span class="b">MSR_IA32_MC0_ADDR</span></a>        <span class="c">0x00000402</span>
<a name="113" /><span class="True">     113:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUMwX01JU0NfMA__"><span class="b">MSR_IA32_MC0_MISC</span></a>        <span class="c">0x00000403</span>
<a name="114" /><span class="True">     114:</span> 
<a name="115" /><span class="True">     115:</span> <span class="k">/* C-state Residency Counters */</span>
<a name="116" /><span class="True">     116:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1BLR19DM19SRVNJREVOQ1lfMA__"><span class="b">MSR_PKG_C3_RESIDENCY</span></a>        <span class="c">0x000003f8</span>
<a name="117" /><span class="True">     117:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1BLR19DNl9SRVNJREVOQ1lfMA__"><span class="b">MSR_PKG_C6_RESIDENCY</span></a>        <span class="c">0x000003f9</span>
<a name="118" /><span class="True">     118:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1BLR19DN19SRVNJREVOQ1lfMA__"><span class="b">MSR_PKG_C7_RESIDENCY</span></a>        <span class="c">0x000003fa</span>
<a name="119" /><span class="True">     119:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0NPUkVfQzNfUkVTSURFTkNZXzA_"><span class="b">MSR_CORE_C3_RESIDENCY</span></a>        <span class="c">0x000003fc</span>
<a name="120" /><span class="True">     120:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0NPUkVfQzZfUkVTSURFTkNZXzA_"><span class="b">MSR_CORE_C6_RESIDENCY</span></a>        <span class="c">0x000003fd</span>
<a name="121" /><span class="True">     121:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0NPUkVfQzdfUkVTSURFTkNZXzA_"><span class="b">MSR_CORE_C7_RESIDENCY</span></a>        <span class="c">0x000003fe</span>
<a name="122" /><span class="True">     122:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1BLR19DMl9SRVNJREVOQ1lfMA__"><span class="b">MSR_PKG_C2_RESIDENCY</span></a>        <span class="c">0x0000060d</span>
<a name="123" /><span class="True">     123:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1BLR19DOF9SRVNJREVOQ1lfMA__"><span class="b">MSR_PKG_C8_RESIDENCY</span></a>        <span class="c">0x00000630</span>
<a name="124" /><span class="True">     124:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1BLR19DOV9SRVNJREVOQ1lfMA__"><span class="b">MSR_PKG_C9_RESIDENCY</span></a>        <span class="c">0x00000631</span>
<a name="125" /><span class="True">     125:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1BLR19DMTBfUkVTSURFTkNZXzA_"><span class="b">MSR_PKG_C10_RESIDENCY</span></a>        <span class="c">0x00000632</span>
<a name="126" /><span class="True">     126:</span> 
<a name="127" /><span class="True">     127:</span> <span class="k">/* Run Time Average Power Limiting (RAPL) Interface */</span>
<a name="128" /><span class="True">     128:</span> 
<a name="129" /><span class="True">     129:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1JBUExfUE9XRVJfVU5JVF8w"><span class="b">MSR_RAPL_POWER_UNIT</span></a>        <span class="c">0x00000606</span>
<a name="130" /><span class="True">     130:</span> 
<a name="131" /><span class="True">     131:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1BLR19QT1dFUl9MSU1JVF8w"><span class="b">MSR_PKG_POWER_LIMIT</span></a>        <span class="c">0x00000610</span>
<a name="132" /><span class="True">     132:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1BLR19FTkVSR1lfU1RBVFVTXzA_"><span class="b">MSR_PKG_ENERGY_STATUS</span></a>        <span class="c">0x00000611</span>
<a name="133" /><span class="True">     133:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1BLR19QRVJGX1NUQVRVU18w"><span class="b">MSR_PKG_PERF_STATUS</span></a>        <span class="c">0x00000613</span>
<a name="134" /><span class="True">     134:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1BLR19QT1dFUl9JTkZPXzA_"><span class="b">MSR_PKG_POWER_INFO</span></a>        <span class="c">0x00000614</span>
<a name="135" /><span class="True">     135:</span> 
<a name="136" /><span class="True">     136:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0RSQU1fUE9XRVJfTElNSVRfMA__"><span class="b">MSR_DRAM_POWER_LIMIT</span></a>        <span class="c">0x00000618</span>
<a name="137" /><span class="True">     137:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0RSQU1fRU5FUkdZX1NUQVRVU18w"><span class="b">MSR_DRAM_ENERGY_STATUS</span></a>        <span class="c">0x00000619</span>
<a name="138" /><span class="True">     138:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0RSQU1fUEVSRl9TVEFUVVNfMA__"><span class="b">MSR_DRAM_PERF_STATUS</span></a>        <span class="c">0x0000061b</span>
<a name="139" /><span class="True">     139:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0RSQU1fUE9XRVJfSU5GT18w"><span class="b">MSR_DRAM_POWER_INFO</span></a>        <span class="c">0x0000061c</span>
<a name="140" /><span class="True">     140:</span> 
<a name="141" /><span class="True">     141:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1BQMF9QT1dFUl9MSU1JVF8w"><span class="b">MSR_PP0_POWER_LIMIT</span></a>        <span class="c">0x00000638</span>
<a name="142" /><span class="True">     142:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1BQMF9FTkVSR1lfU1RBVFVTXzA_"><span class="b">MSR_PP0_ENERGY_STATUS</span></a>        <span class="c">0x00000639</span>
<a name="143" /><span class="True">     143:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1BQMF9QT0xJQ1lfMA__"><span class="b">MSR_PP0_POLICY</span></a>            <span class="c">0x0000063a</span>
<a name="144" /><span class="True">     144:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1BQMF9QRVJGX1NUQVRVU18w"><span class="b">MSR_PP0_PERF_STATUS</span></a>        <span class="c">0x0000063b</span>
<a name="145" /><span class="True">     145:</span> 
<a name="146" /><span class="True">     146:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1BQMV9QT1dFUl9MSU1JVF8w"><span class="b">MSR_PP1_POWER_LIMIT</span></a>        <span class="c">0x00000640</span>
<a name="147" /><span class="True">     147:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1BQMV9FTkVSR1lfU1RBVFVTXzA_"><span class="b">MSR_PP1_ENERGY_STATUS</span></a>        <span class="c">0x00000641</span>
<a name="148" /><span class="True">     148:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1BQMV9QT0xJQ1lfMA__"><span class="b">MSR_PP1_POLICY</span></a>            <span class="c">0x00000642</span>
<a name="149" /><span class="True">     149:</span> 
<a name="150" /><span class="True">     150:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0NPUkVfQzFfUkVTXzA_"><span class="b">MSR_CORE_C1_RES</span></a>            <span class="c">0x00000660</span>
<a name="151" /><span class="True">     151:</span> 
<a name="152" /><span class="True">     152:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X01DMF9NQVNLXzA_"><span class="b">MSR_AMD64_MC0_MASK</span></a>        <span class="c">0xc0010044</span>
<a name="153" /><span class="True">     153:</span> 
<a name="154" /><span class="True">     154:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUN4X0NUTF8w"><span class="b">MSR_IA32_MCx_CTL</span></a><span class="f">(</span><span class="b">x</span><span class="f">)</span>        <span class="f">(</span><a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUMwX0NUTF8w"><span class="b">MSR_IA32_MC0_CTL</span></a> <span class="f">+</span> <span class="c">4</span><span class="f">*</span><span class="f">(</span><span class="b">x</span><span class="f">)</span><span class="f">)</span>
<a name="155" /><span class="True">     155:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUN4X1NUQVRVU18w"><span class="b">MSR_IA32_MCx_STATUS</span></a><span class="f">(</span><span class="b">x</span><span class="f">)</span>        <span class="f">(</span><a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUMwX1NUQVRVU18w"><span class="b">MSR_IA32_MC0_STATUS</span></a> <span class="f">+</span> <span class="c">4</span><span class="f">*</span><span class="f">(</span><span class="b">x</span><span class="f">)</span><span class="f">)</span>
<a name="156" /><span class="True">     156:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUN4X0FERFJfMA__"><span class="b">MSR_IA32_MCx_ADDR</span></a><span class="f">(</span><span class="b">x</span><span class="f">)</span>        <span class="f">(</span><a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUMwX0FERFJfMA__"><span class="b">MSR_IA32_MC0_ADDR</span></a> <span class="f">+</span> <span class="c">4</span><span class="f">*</span><span class="f">(</span><span class="b">x</span><span class="f">)</span><span class="f">)</span>
<a name="157" /><span class="True">     157:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUN4X01JU0NfMA__"><span class="b">MSR_IA32_MCx_MISC</span></a><span class="f">(</span><span class="b">x</span><span class="f">)</span>        <span class="f">(</span><a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUMwX01JU0NfMA__"><span class="b">MSR_IA32_MC0_MISC</span></a> <span class="f">+</span> <span class="c">4</span><span class="f">*</span><span class="f">(</span><span class="b">x</span><span class="f">)</span><span class="f">)</span>
<a name="158" /><span class="True">     158:</span> 
<a name="159" /><span class="True">     159:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X01DeF9NQVNLXzA_"><span class="b">MSR_AMD64_MCx_MASK</span></a><span class="f">(</span><span class="b">x</span><span class="f">)</span>        <span class="f">(</span><a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X01DMF9NQVNLXzA_"><span class="b">MSR_AMD64_MC0_MASK</span></a> <span class="f">+</span> <span class="f">(</span><span class="b">x</span><span class="f">)</span><span class="f">)</span>
<a name="160" /><span class="True">     160:</span> 
<a name="161" /><span class="True">     161:</span> <span class="k">/* These are consecutive and not in the normal 4er MCE bank block */</span>
<a name="162" /><span class="True">     162:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUMwX0NUTDJfMA__"><span class="b">MSR_IA32_MC0_CTL2</span></a>        <span class="c">0x00000280</span>
<a name="163" /><span class="True">     163:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUN4X0NUTDJfMA__"><span class="b">MSR_IA32_MCx_CTL2</span></a><span class="f">(</span><span class="b">x</span><span class="f">)</span>        <span class="f">(</span><a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUMwX0NUTDJfMA__"><span class="b">MSR_IA32_MC0_CTL2</span></a> <span class="f">+</span> <span class="f">(</span><span class="b">x</span><span class="f">)</span><span class="f">)</span>
<a name="164" /><span class="True">     164:</span> 
<a name="165" /><span class="True">     165:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A2X1BFUkZDVFIwXzA_"><span class="b">MSR_P6_PERFCTR0</span></a>            <span class="c">0x000000c1</span>
<a name="166" /><span class="True">     166:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A2X1BFUkZDVFIxXzA_"><span class="b">MSR_P6_PERFCTR1</span></a>            <span class="c">0x000000c2</span>
<a name="167" /><span class="True">     167:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A2X0VWTlRTRUwwXzA_"><span class="b">MSR_P6_EVNTSEL0</span></a>            <span class="c">0x00000186</span>
<a name="168" /><span class="True">     168:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A2X0VWTlRTRUwxXzA_"><span class="b">MSR_P6_EVNTSEL1</span></a>            <span class="c">0x00000187</span>
<a name="169" /><span class="True">     169:</span> 
<a name="170" /><span class="True">     170:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0tOQ19QRVJGQ1RSMF8w"><span class="b">MSR_KNC_PERFCTR0</span></a>               <span class="c">0x00000020</span>
<a name="171" /><span class="True">     171:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0tOQ19QRVJGQ1RSMV8w"><span class="b">MSR_KNC_PERFCTR1</span></a>               <span class="c">0x00000021</span>
<a name="172" /><span class="True">     172:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0tOQ19FVk5UU0VMMF8w"><span class="b">MSR_KNC_EVNTSEL0</span></a>               <span class="c">0x00000028</span>
<a name="173" /><span class="True">     173:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0tOQ19FVk5UU0VMMV8w"><span class="b">MSR_KNC_EVNTSEL1</span></a>               <span class="c">0x00000029</span>
<a name="174" /><span class="True">     174:</span> 
<a name="175" /><span class="True">     175:</span> <span class="k">/* Alternative perfctr range with full access. */</span>
<a name="176" /><span class="True">     176:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfUE1DMF8w"><span class="b">MSR_IA32_PMC0</span></a>            <span class="c">0x000004c1</span>
<a name="177" /><span class="True">     177:</span> 
<a name="178" /><span class="True">     178:</span> <span class="k">/* AMD64 MSRs. Not complete. See the architecture manual for a more</span>
<a name="179" /><span class="True">     179:</span> <span class="k">   complete list. */</span>
<a name="180" /><span class="True">     180:</span> 
<a name="181" /><span class="True">     181:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X1BBVENIX0xFVkVMXzA_"><span class="b">MSR_AMD64_PATCH_LEVEL</span></a>        <span class="c">0x0000008b</span>
<a name="182" /><span class="True">     182:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X1RTQ19SQVRJT18w"><span class="b">MSR_AMD64_TSC_RATIO</span></a>        <span class="c">0xc0000104</span>
<a name="183" /><span class="True">     183:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X05CX0NGR18w"><span class="b">MSR_AMD64_NB_CFG</span></a>        <span class="c">0xc001001f</span>
<a name="184" /><span class="True">     184:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X1BBVENIX0xPQURFUl8w"><span class="b">MSR_AMD64_PATCH_LOADER</span></a>        <span class="c">0xc0010020</span>
<a name="185" /><span class="True">     185:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X09TVldfSURfTEVOR1RIXzA_"><span class="b">MSR_AMD64_OSVW_ID_LENGTH</span></a>    <span class="c">0xc0010140</span>
<a name="186" /><span class="True">     186:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X09TVldfU1RBVFVTXzA_"><span class="b">MSR_AMD64_OSVW_STATUS</span></a>        <span class="c">0xc0010141</span>
<a name="187" /><span class="True">     187:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0RDX0NGR18w"><span class="b">MSR_AMD64_DC_CFG</span></a>        <span class="c">0xc0011022</span>
<a name="188" /><span class="True">     188:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0JVX0NGRzJfMA__"><span class="b">MSR_AMD64_BU_CFG2</span></a>        <span class="c">0xc001102a</span>
<a name="189" /><span class="True">     189:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0lCU0ZFVENIQ1RMXzA_"><span class="b">MSR_AMD64_IBSFETCHCTL</span></a>        <span class="c">0xc0011030</span>
<a name="190" /><span class="True">     190:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0lCU0ZFVENITElOQURfMA__"><span class="b">MSR_AMD64_IBSFETCHLINAD</span></a>        <span class="c">0xc0011031</span>
<a name="191" /><span class="True">     191:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0lCU0ZFVENIUEhZU0FEXzA_"><span class="b">MSR_AMD64_IBSFETCHPHYSAD</span></a>    <span class="c">0xc0011032</span>
<a name="192" /><span class="True">     192:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0lCU0ZFVENIX1JFR19DT1VOVF8w"><span class="b">MSR_AMD64_IBSFETCH_REG_COUNT</span></a>    <span class="c">3</span>
<a name="193" /><span class="True">     193:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0lCU0ZFVENIX1JFR19NQVNLXzA_"><span class="b">MSR_AMD64_IBSFETCH_REG_MASK</span></a>    <span class="f">(</span><span class="f">(</span><span class="c">1UL</span><span class="f">&lt;&lt;</span><a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0lCU0ZFVENIX1JFR19DT1VOVF8w"><span class="b">MSR_AMD64_IBSFETCH_REG_COUNT</span></a><span class="f">)</span><span class="f">-</span><span class="c">1</span><span class="f">)</span>
<a name="194" /><span class="True">     194:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0lCU09QQ1RMXzA_"><span class="b">MSR_AMD64_IBSOPCTL</span></a>        <span class="c">0xc0011033</span>
<a name="195" /><span class="True">     195:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0lCU09QUklQXzA_"><span class="b">MSR_AMD64_IBSOPRIP</span></a>        <span class="c">0xc0011034</span>
<a name="196" /><span class="True">     196:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0lCU09QREFUQV8w"><span class="b">MSR_AMD64_IBSOPDATA</span></a>        <span class="c">0xc0011035</span>
<a name="197" /><span class="True">     197:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0lCU09QREFUQTJfMA__"><span class="b">MSR_AMD64_IBSOPDATA2</span></a>        <span class="c">0xc0011036</span>
<a name="198" /><span class="True">     198:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0lCU09QREFUQTNfMA__"><span class="b">MSR_AMD64_IBSOPDATA3</span></a>        <span class="c">0xc0011037</span>
<a name="199" /><span class="True">     199:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0lCU0RDTElOQURfMA__"><span class="b">MSR_AMD64_IBSDCLINAD</span></a>        <span class="c">0xc0011038</span>
<a name="200" /><span class="True">     200:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0lCU0RDUEhZU0FEXzA_"><span class="b">MSR_AMD64_IBSDCPHYSAD</span></a>        <span class="c">0xc0011039</span>
<a name="201" /><span class="True">     201:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0lCU09QX1JFR19DT1VOVF8w"><span class="b">MSR_AMD64_IBSOP_REG_COUNT</span></a>    <span class="c">7</span>
<a name="202" /><span class="True">     202:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0lCU09QX1JFR19NQVNLXzA_"><span class="b">MSR_AMD64_IBSOP_REG_MASK</span></a>    <span class="f">(</span><span class="f">(</span><span class="c">1UL</span><span class="f">&lt;&lt;</span><a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0lCU09QX1JFR19DT1VOVF8w"><span class="b">MSR_AMD64_IBSOP_REG_COUNT</span></a><span class="f">)</span><span class="f">-</span><span class="c">1</span><span class="f">)</span>
<a name="203" /><span class="True">     203:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0lCU0NUTF8w"><span class="b">MSR_AMD64_IBSCTL</span></a>        <span class="c">0xc001103a</span>
<a name="204" /><span class="True">     204:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0lCU0JSVEFSR0VUXzA_"><span class="b">MSR_AMD64_IBSBRTARGET</span></a>        <span class="c">0xc001103b</span>
<a name="205" /><span class="True">     205:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRDY0X0lCU19SRUdfQ09VTlRfTUFYXzA_"><span class="b">MSR_AMD64_IBS_REG_COUNT_MAX</span></a>    <span class="c">8</span> <span class="k">/* includes MSR_AMD64_IBSBRTARGET */</span>
<a name="206" /><span class="True">     206:</span> 
<a name="207" /><span class="True">     207:</span> <span class="k">/* Fam 16h MSRs */</span>
<a name="208" /><span class="True">     208:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0YxNkhfTDJJX1BFUkZfQ1RMXzA_"><span class="b">MSR_F16H_L2I_PERF_CTL</span></a>        <span class="c">0xc0010230</span>
<a name="209" /><span class="True">     209:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0YxNkhfTDJJX1BFUkZfQ1RSXzA_"><span class="b">MSR_F16H_L2I_PERF_CTR</span></a>        <span class="c">0xc0010231</span>
<a name="210" /><span class="True">     210:</span> 
<a name="211" /><span class="True">     211:</span> <span class="k">/* Fam 15h MSRs */</span>
<a name="212" /><span class="True">     212:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0YxNUhfUEVSRl9DVExfMA__"><span class="b">MSR_F15H_PERF_CTL</span></a>        <span class="c">0xc0010200</span>
<a name="213" /><span class="True">     213:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0YxNUhfUEVSRl9DVFJfMA__"><span class="b">MSR_F15H_PERF_CTR</span></a>        <span class="c">0xc0010201</span>
<a name="214" /><span class="True">     214:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0YxNUhfTkJfUEVSRl9DVExfMA__"><span class="b">MSR_F15H_NB_PERF_CTL</span></a>        <span class="c">0xc0010240</span>
<a name="215" /><span class="True">     215:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0YxNUhfTkJfUEVSRl9DVFJfMA__"><span class="b">MSR_F15H_NB_PERF_CTR</span></a>        <span class="c">0xc0010241</span>
<a name="216" /><span class="True">     216:</span> 
<a name="217" /><span class="True">     217:</span> <span class="k">/* Fam 10h MSRs */</span>
<a name="218" /><span class="True">     218:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0ZBTTEwSF9NTUlPX0NPTkZfQkFTRV8w"><span class="b">MSR_FAM10H_MMIO_CONF_BASE</span></a>    <span class="c">0xc0010058</span>
<a name="219" /><span class="True">     219:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_RkFNMTBIX01NSU9fQ09ORl9FTkFCTEVfMA__"><span class="b">FAM10H_MMIO_CONF_ENABLE</span></a>        <span class="f">(</span><span class="c">1</span><span class="f">&lt;&lt;</span><span class="c">0</span><span class="f">)</span>
<a name="220" /><span class="True">     220:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_RkFNMTBIX01NSU9fQ09ORl9CVVNSQU5HRV9NQVNLXzA_"><span class="b">FAM10H_MMIO_CONF_BUSRANGE_MASK</span></a>    <span class="c">0xf</span>
<a name="221" /><span class="True">     221:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_RkFNMTBIX01NSU9fQ09ORl9CVVNSQU5HRV9TSElGVF8w"><span class="b">FAM10H_MMIO_CONF_BUSRANGE_SHIFT</span></a> <span class="c">2</span>
<a name="222" /><span class="True">     222:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_RkFNMTBIX01NSU9fQ09ORl9CQVNFX01BU0tfMA__"><span class="b">FAM10H_MMIO_CONF_BASE_MASK</span></a>    <span class="c">0xfffffffULL</span>
<a name="223" /><span class="True">     223:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_RkFNMTBIX01NSU9fQ09ORl9CQVNFX1NISUZUXzA_"><span class="b">FAM10H_MMIO_CONF_BASE_SHIFT</span></a>    <span class="c">20</span>
<a name="224" /><span class="True">     224:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0ZBTTEwSF9OT0RFX0lEXzA_"><span class="b">MSR_FAM10H_NODE_ID</span></a>        <span class="c">0xc001100c</span>
<a name="225" /><span class="True">     225:</span> 
<a name="226" /><span class="True">     226:</span> <span class="k">/* K8 MSRs */</span>
<a name="227" /><span class="True">     227:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s4X1RPUF9NRU0xXzA_"><span class="b">MSR_K8_TOP_MEM1</span></a>            <span class="c">0xc001001a</span>
<a name="228" /><span class="True">     228:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s4X1RPUF9NRU0yXzA_"><span class="b">MSR_K8_TOP_MEM2</span></a>            <span class="c">0xc001001d</span>
<a name="229" /><span class="True">     229:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s4X1NZU0NGR18w"><span class="b">MSR_K8_SYSCFG</span></a>            <span class="c">0xc0010010</span>
<a name="230" /><span class="True">     230:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s4X0lOVF9QRU5ESU5HX01TR18w"><span class="b">MSR_K8_INT_PENDING_MSG</span></a>        <span class="c">0xc0010055</span>
<a name="231" /><span class="True">     231:</span> <span class="k">/* C1E active bits in int pending message */</span>
<a name="232" /><span class="True">     232:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SzhfSU5UUF9DMUVfQUNUSVZFX01BU0tfMA__"><span class="b">K8_INTP_C1E_ACTIVE_MASK</span></a>        <span class="c">0x18000000</span>
<a name="233" /><span class="True">     233:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s4X1RTRUdfQUREUl8w"><span class="b">MSR_K8_TSEG_ADDR</span></a>        <span class="c">0xc0010112</span>
<a name="234" /><span class="True">     234:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SzhfTVRSUkZJWFJBTkdFX0RSQU1fRU5BQkxFXzA_"><span class="b">K8_MTRRFIXRANGE_DRAM_ENABLE</span></a>    <span class="c">0x00040000</span> <span class="k">/* MtrrFixDramEn bit    */</span>
<a name="235" /><span class="True">     235:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SzhfTVRSUkZJWFJBTkdFX0RSQU1fTU9ESUZZXzA_"><span class="b">K8_MTRRFIXRANGE_DRAM_MODIFY</span></a>    <span class="c">0x00080000</span> <span class="k">/* MtrrFixDramModEn bit */</span>
<a name="236" /><span class="True">     236:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SzhfTVRSUl9SRE1FTV9XUk1FTV9NQVNLXzA_"><span class="b">K8_MTRR_RDMEM_WRMEM_MASK</span></a>    <span class="c">0x18181818</span> <span class="k">/* Mask: RdMem|WrMem    */</span>
<a name="237" /><span class="True">     237:</span> 
<a name="238" /><span class="True">     238:</span> <span class="k">/* K7 MSRs */</span>
<a name="239" /><span class="True">     239:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s3X0VWTlRTRUwwXzA_"><span class="b">MSR_K7_EVNTSEL0</span></a>            <span class="c">0xc0010000</span>
<a name="240" /><span class="True">     240:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s3X1BFUkZDVFIwXzA_"><span class="b">MSR_K7_PERFCTR0</span></a>            <span class="c">0xc0010004</span>
<a name="241" /><span class="True">     241:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s3X0VWTlRTRUwxXzA_"><span class="b">MSR_K7_EVNTSEL1</span></a>            <span class="c">0xc0010001</span>
<a name="242" /><span class="True">     242:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s3X1BFUkZDVFIxXzA_"><span class="b">MSR_K7_PERFCTR1</span></a>            <span class="c">0xc0010005</span>
<a name="243" /><span class="True">     243:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s3X0VWTlRTRUwyXzA_"><span class="b">MSR_K7_EVNTSEL2</span></a>            <span class="c">0xc0010002</span>
<a name="244" /><span class="True">     244:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s3X1BFUkZDVFIyXzA_"><span class="b">MSR_K7_PERFCTR2</span></a>            <span class="c">0xc0010006</span>
<a name="245" /><span class="True">     245:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s3X0VWTlRTRUwzXzA_"><span class="b">MSR_K7_EVNTSEL3</span></a>            <span class="c">0xc0010003</span>
<a name="246" /><span class="True">     246:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s3X1BFUkZDVFIzXzA_"><span class="b">MSR_K7_PERFCTR3</span></a>            <span class="c">0xc0010007</span>
<a name="247" /><span class="True">     247:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s3X0NMS19DVExfMA__"><span class="b">MSR_K7_CLK_CTL</span></a>            <span class="c">0xc001001b</span>
<a name="248" /><span class="True">     248:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s3X0hXQ1JfMA__"><span class="b">MSR_K7_HWCR</span></a>            <span class="c">0xc0010015</span>
<a name="249" /><span class="True">     249:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s3X0ZJRF9WSURfQ1RMXzA_"><span class="b">MSR_K7_FID_VID_CTL</span></a>        <span class="c">0xc0010041</span>
<a name="250" /><span class="True">     250:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s3X0ZJRF9WSURfU1RBVFVTXzA_"><span class="b">MSR_K7_FID_VID_STATUS</span></a>        <span class="c">0xc0010042</span>
<a name="251" /><span class="True">     251:</span> 
<a name="252" /><span class="True">     252:</span> <span class="k">/* K6 MSRs */</span>
<a name="253" /><span class="True">     253:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s2X1dIQ1JfMA__"><span class="b">MSR_K6_WHCR</span></a>            <span class="c">0xc0000082</span>
<a name="254" /><span class="True">     254:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s2X1VXQ0NSXzA_"><span class="b">MSR_K6_UWCCR</span></a>            <span class="c">0xc0000085</span>
<a name="255" /><span class="True">     255:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s2X0VQTVJfMA__"><span class="b">MSR_K6_EPMR</span></a>            <span class="c">0xc0000086</span>
<a name="256" /><span class="True">     256:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s2X1BTT1JfMA__"><span class="b">MSR_K6_PSOR</span></a>            <span class="c">0xc0000087</span>
<a name="257" /><span class="True">     257:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0s2X1BGSVJfMA__"><span class="b">MSR_K6_PFIR</span></a>            <span class="c">0xc0000088</span>
<a name="258" /><span class="True">     258:</span> 
<a name="259" /><span class="True">     259:</span> <span class="k">/* Centaur-Hauls/IDT defined MSRs. */</span>
<a name="260" /><span class="True">     260:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lEVF9GQ1IxXzA_"><span class="b">MSR_IDT_FCR1</span></a>            <span class="c">0x00000107</span>
<a name="261" /><span class="True">     261:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lEVF9GQ1IyXzA_"><span class="b">MSR_IDT_FCR2</span></a>            <span class="c">0x00000108</span>
<a name="262" /><span class="True">     262:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lEVF9GQ1IzXzA_"><span class="b">MSR_IDT_FCR3</span></a>            <span class="c">0x00000109</span>
<a name="263" /><span class="True">     263:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lEVF9GQ1I0XzA_"><span class="b">MSR_IDT_FCR4</span></a>            <span class="c">0x0000010a</span>
<a name="264" /><span class="True">     264:</span> 
<a name="265" /><span class="True">     265:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lEVF9NQ1IwXzA_"><span class="b">MSR_IDT_MCR0</span></a>            <span class="c">0x00000110</span>
<a name="266" /><span class="True">     266:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lEVF9NQ1IxXzA_"><span class="b">MSR_IDT_MCR1</span></a>            <span class="c">0x00000111</span>
<a name="267" /><span class="True">     267:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lEVF9NQ1IyXzA_"><span class="b">MSR_IDT_MCR2</span></a>            <span class="c">0x00000112</span>
<a name="268" /><span class="True">     268:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lEVF9NQ1IzXzA_"><span class="b">MSR_IDT_MCR3</span></a>            <span class="c">0x00000113</span>
<a name="269" /><span class="True">     269:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lEVF9NQ1I0XzA_"><span class="b">MSR_IDT_MCR4</span></a>            <span class="c">0x00000114</span>
<a name="270" /><span class="True">     270:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lEVF9NQ1I1XzA_"><span class="b">MSR_IDT_MCR5</span></a>            <span class="c">0x00000115</span>
<a name="271" /><span class="True">     271:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lEVF9NQ1I2XzA_"><span class="b">MSR_IDT_MCR6</span></a>            <span class="c">0x00000116</span>
<a name="272" /><span class="True">     272:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lEVF9NQ1I3XzA_"><span class="b">MSR_IDT_MCR7</span></a>            <span class="c">0x00000117</span>
<a name="273" /><span class="True">     273:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lEVF9NQ1JfQ1RSTF8w"><span class="b">MSR_IDT_MCR_CTRL</span></a>        <span class="c">0x00000120</span>
<a name="274" /><span class="True">     274:</span> 
<a name="275" /><span class="True">     275:</span> <span class="k">/* VIA Cyrix defined MSRs*/</span>
<a name="276" /><span class="True">     276:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1ZJQV9GQ1JfMA__"><span class="b">MSR_VIA_FCR</span></a>            <span class="c">0x00001107</span>
<a name="277" /><span class="True">     277:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1ZJQV9MT05HSEFVTF8w"><span class="b">MSR_VIA_LONGHAUL</span></a>        <span class="c">0x0000110a</span>
<a name="278" /><span class="True">     278:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1ZJQV9STkdfMA__"><span class="b">MSR_VIA_RNG</span></a>            <span class="c">0x0000110b</span>
<a name="279" /><span class="True">     279:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1ZJQV9CQ1IyXzA_"><span class="b">MSR_VIA_BCR2</span></a>            <span class="c">0x00001147</span>
<a name="280" /><span class="True">     280:</span> 
<a name="281" /><span class="True">     281:</span> <span class="k">/* Transmeta defined MSRs */</span>
<a name="282" /><span class="True">     282:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1RNVEFfTE9OR1JVTl9DVFJMXzA_"><span class="b">MSR_TMTA_LONGRUN_CTRL</span></a>        <span class="c">0x80868010</span>
<a name="283" /><span class="True">     283:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1RNVEFfTE9OR1JVTl9GTEFHU18w"><span class="b">MSR_TMTA_LONGRUN_FLAGS</span></a>        <span class="c">0x80868011</span>
<a name="284" /><span class="True">     284:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1RNVEFfTFJUSV9SRUFET1VUXzA_"><span class="b">MSR_TMTA_LRTI_READOUT</span></a>        <span class="c">0x80868018</span>
<a name="285" /><span class="True">     285:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1RNVEFfTFJUSV9WT0xUX01IWl8w"><span class="b">MSR_TMTA_LRTI_VOLT_MHZ</span></a>        <span class="c">0x8086801a</span>
<a name="286" /><span class="True">     286:</span> 
<a name="287" /><span class="True">     287:</span> <span class="k">/* Intel defined MSRs. */</span>
<a name="288" /><span class="True">     288:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfUDVfTUNfQUREUl8w"><span class="b">MSR_IA32_P5_MC_ADDR</span></a>        <span class="c">0x00000000</span>
<a name="289" /><span class="True">     289:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfUDVfTUNfVFlQRV8w"><span class="b">MSR_IA32_P5_MC_TYPE</span></a>        <span class="c">0x00000001</span>
<a name="290" /><span class="True">     290:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVFNDXzA_"><span class="b">MSR_IA32_TSC</span></a>            <span class="c">0x00000010</span>
<a name="291" /><span class="True">     291:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfUExBVEZPUk1fSURfMA__"><span class="b">MSR_IA32_PLATFORM_ID</span></a>        <span class="c">0x00000017</span>
<a name="292" /><span class="True">     292:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfRUJMX0NSX1BPV0VST05fMA__"><span class="b">MSR_IA32_EBL_CR_POWERON</span></a>        <span class="c">0x0000002a</span>
<a name="293" /><span class="True">     293:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0VCQ19GUkVRVUVOQ1lfSURfMA__"><span class="b">MSR_EBC_FREQUENCY_ID</span></a>        <span class="c">0x0000002c</span>
<a name="294" /><span class="True">     294:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1NNSV9DT1VOVF8w"><span class="b">MSR_SMI_COUNT</span></a>            <span class="c">0x00000034</span>
<a name="295" /><span class="True">     295:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfRkVBVFVSRV9DT05UUk9MXzA_"><span class="b">MSR_IA32_FEATURE_CONTROL</span></a>        <span class="c">0x0000003a</span>
<a name="296" /><span class="True">     296:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVFNDX0FESlVTVF8w"><span class="b">MSR_IA32_TSC_ADJUST</span></a>             <span class="c">0x0000003b</span>
<a name="297" /><span class="True">     297:</span> 
<a name="298" /><span class="True">     298:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_RkVBVFVSRV9DT05UUk9MX0xPQ0tFRF8w"><span class="b">FEATURE_CONTROL_LOCKED</span></a>                <span class="f">(</span><span class="c">1</span><span class="f">&lt;&lt;</span><span class="c">0</span><span class="f">)</span>
<a name="299" /><span class="True">     299:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_RkVBVFVSRV9DT05UUk9MX1ZNWE9OX0VOQUJMRURfSU5TSURFX1NNWF8w"><span class="b">FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX</span></a>    <span class="f">(</span><span class="c">1</span><span class="f">&lt;&lt;</span><span class="c">1</span><span class="f">)</span>
<a name="300" /><span class="True">     300:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_RkVBVFVSRV9DT05UUk9MX1ZNWE9OX0VOQUJMRURfT1VUU0lERV9TTVhfMA__"><span class="b">FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX</span></a>    <span class="f">(</span><span class="c">1</span><span class="f">&lt;&lt;</span><span class="c">2</span><span class="f">)</span>
<a name="301" /><span class="True">     301:</span> 
<a name="302" /><span class="True">     302:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_TVNSX0lBMzJfQVBJQ0JBU0VfMA__"><span class="b">MSR_IA32_APICBASE</span></a>        <span class="c">0x0000001b</span>
<a name="303" /><span class="True">     303:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfQVBJQ0JBU0VfQlNQXzA_"><span class="b">MSR_IA32_APICBASE_BSP</span></a>        <span class="f">(</span><span class="c">1</span><span class="f">&lt;&lt;</span><span class="c">8</span><span class="f">)</span>
<a name="304" /><span class="True">     304:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfQVBJQ0JBU0VfRU5BQkxFXzA_"><span class="b">MSR_IA32_APICBASE_ENABLE</span></a>    <span class="f">(</span><span class="c">1</span><span class="f">&lt;&lt;</span><span class="c">11</span><span class="f">)</span>
<a name="305" /><span class="True">     305:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfQVBJQ0JBU0VfQkFTRV8w"><span class="b">MSR_IA32_APICBASE_BASE</span></a>        <span class="f">(</span><span class="c">0xfffff</span><span class="f">&lt;&lt;</span><span class="c">12</span><span class="f">)</span>
<a name="306" /><span class="True">     306:</span> 
<a name="307" /><span class="True">     307:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVFNDREVBRExJTkVfMA__"><span class="b">MSR_IA32_TSCDEADLINE</span></a>        <span class="c">0x000006e0</span>
<a name="308" /><span class="True">     308:</span> 
<a name="309" /><span class="True">     309:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVUNPREVfV1JJVEVfMA__"><span class="b">MSR_IA32_UCODE_WRITE</span></a>        <span class="c">0x00000079</span>
<a name="310" /><span class="True">     310:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVUNPREVfUkVWXzA_"><span class="b">MSR_IA32_UCODE_REV</span></a>        <span class="c">0x0000008b</span>
<a name="311" /><span class="True">     311:</span> 
<a name="312" /><span class="True">     312:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfUEVSRl9TVEFUVVNfMA__"><span class="b">MSR_IA32_PERF_STATUS</span></a>        <span class="c">0x00000198</span>
<a name="313" /><span class="True">     313:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfUEVSRl9DVExfMA__"><span class="b">MSR_IA32_PERF_CTL</span></a>        <span class="c">0x00000199</span>
<a name="314" /><span class="True">     314:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRF9QU1RBVEVfREVGX0JBU0VfMA__"><span class="b">MSR_AMD_PSTATE_DEF_BASE</span></a>        <span class="c">0xc0010064</span>
<a name="315" /><span class="True">     315:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRF9QRVJGX1NUQVRVU18w"><span class="b">MSR_AMD_PERF_STATUS</span></a>        <span class="c">0xc0010063</span>
<a name="316" /><span class="True">     316:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0FNRF9QRVJGX0NUTF8w"><span class="b">MSR_AMD_PERF_CTL</span></a>        <span class="c">0xc0010062</span>
<a name="317" /><span class="True">     317:</span> 
<a name="318" /><span class="True">     318:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTVBFUkZfMA__"><span class="b">MSR_IA32_MPERF</span></a>            <span class="c">0x000000e7</span>
<a name="319" /><span class="True">     319:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfQVBFUkZfMA__"><span class="b">MSR_IA32_APERF</span></a>            <span class="c">0x000000e8</span>
<a name="320" /><span class="True">     320:</span> 
<a name="321" /><span class="True">     321:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVEhFUk1fQ09OVFJPTF8w"><span class="b">MSR_IA32_THERM_CONTROL</span></a>        <span class="c">0x0000019a</span>
<a name="322" /><span class="True">     322:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVEhFUk1fSU5URVJSVVBUXzA_"><span class="b">MSR_IA32_THERM_INTERRUPT</span></a>    <span class="c">0x0000019b</span>
<a name="323" /><span class="True">     323:</span> 
<a name="324" /><span class="True">     324:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_VEhFUk1fSU5UX0hJR0hfRU5BQkxFXzA_"><span class="b">THERM_INT_HIGH_ENABLE</span></a>        <span class="f">(</span><span class="c">1</span> <span class="f">&lt;&lt;</span> <span class="c">0</span><span class="f">)</span>
<a name="325" /><span class="True">     325:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_VEhFUk1fSU5UX0xPV19FTkFCTEVfMA__"><span class="b">THERM_INT_LOW_ENABLE</span></a>        <span class="f">(</span><span class="c">1</span> <span class="f">&lt;&lt;</span> <span class="c">1</span><span class="f">)</span>
<a name="326" /><span class="True">     326:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_VEhFUk1fSU5UX1BMTl9FTkFCTEVfMA__"><span class="b">THERM_INT_PLN_ENABLE</span></a>        <span class="f">(</span><span class="c">1</span> <span class="f">&lt;&lt;</span> <span class="c">24</span><span class="f">)</span>
<a name="327" /><span class="True">     327:</span> 
<a name="328" /><span class="True">     328:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVEhFUk1fU1RBVFVTXzA_"><span class="b">MSR_IA32_THERM_STATUS</span></a>        <span class="c">0x0000019c</span>
<a name="329" /><span class="True">     329:</span> 
<a name="330" /><span class="True">     330:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_VEhFUk1fU1RBVFVTX1BST0NIT1RfMA__"><span class="b">THERM_STATUS_PROCHOT</span></a>        <span class="f">(</span><span class="c">1</span> <span class="f">&lt;&lt;</span> <span class="c">0</span><span class="f">)</span>
<a name="331" /><span class="True">     331:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_VEhFUk1fU1RBVFVTX1BPV0VSX0xJTUlUXzA_"><span class="b">THERM_STATUS_POWER_LIMIT</span></a>    <span class="f">(</span><span class="c">1</span> <span class="f">&lt;&lt;</span> <span class="c">10</span><span class="f">)</span>
<a name="332" /><span class="True">     332:</span> 
<a name="333" /><span class="True">     333:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1RIRVJNMl9DVExfMA__"><span class="b">MSR_THERM2_CTL</span></a>            <span class="c">0x0000019d</span>
<a name="334" /><span class="True">     334:</span> 
<a name="335" /><span class="True">     335:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1RIRVJNMl9DVExfVE1fU0VMRUNUXzA_"><span class="b">MSR_THERM2_CTL_TM_SELECT</span></a>    <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">16</span><span class="f">)</span>
<a name="336" /><span class="True">     336:</span> 
<a name="337" /><span class="True">     337:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfMA__"><span class="b">MSR_IA32_MISC_ENABLE</span></a>        <span class="c">0x000001a0</span>
<a name="338" /><span class="True">     338:</span> 
<a name="339" /><span class="True">     339:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVEVNUEVSQVRVUkVfVEFSR0VUXzA_"><span class="b">MSR_IA32_TEMPERATURE_TARGET</span></a>    <span class="c">0x000001a2</span>
<a name="340" /><span class="True">     340:</span> 
<a name="341" /><span class="True">     341:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfRU5FUkdZX1BFUkZfQklBU18w"><span class="b">MSR_IA32_ENERGY_PERF_BIAS</span></a>    <span class="c">0x000001b0</span>
<a name="342" /><span class="True">     342:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_RU5FUkdZX1BFUkZfQklBU19QRVJGT1JNQU5DRV8w"><span class="b">ENERGY_PERF_BIAS_PERFORMANCE</span></a>    <span class="c">0</span>
<a name="343" /><span class="True">     343:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_RU5FUkdZX1BFUkZfQklBU19OT1JNQUxfMA__"><span class="b">ENERGY_PERF_BIAS_NORMAL</span></a>        <span class="c">6</span>
<a name="344" /><span class="True">     344:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_RU5FUkdZX1BFUkZfQklBU19QT1dFUlNBVkVfMA__"><span class="b">ENERGY_PERF_BIAS_POWERSAVE</span></a>    <span class="c">15</span>
<a name="345" /><span class="True">     345:</span> 
<a name="346" /><span class="True">     346:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfUEFDS0FHRV9USEVSTV9TVEFUVVNfMA__"><span class="b">MSR_IA32_PACKAGE_THERM_STATUS</span></a>        <span class="c">0x000001b1</span>
<a name="347" /><span class="True">     347:</span> 
<a name="348" /><span class="True">     348:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_UEFDS0FHRV9USEVSTV9TVEFUVVNfUFJPQ0hPVF8w"><span class="b">PACKAGE_THERM_STATUS_PROCHOT</span></a>        <span class="f">(</span><span class="c">1</span> <span class="f">&lt;&lt;</span> <span class="c">0</span><span class="f">)</span>
<a name="349" /><span class="True">     349:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_UEFDS0FHRV9USEVSTV9TVEFUVVNfUE9XRVJfTElNSVRfMA__"><span class="b">PACKAGE_THERM_STATUS_POWER_LIMIT</span></a>    <span class="f">(</span><span class="c">1</span> <span class="f">&lt;&lt;</span> <span class="c">10</span><span class="f">)</span>
<a name="350" /><span class="True">     350:</span> 
<a name="351" /><span class="True">     351:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfUEFDS0FHRV9USEVSTV9JTlRFUlJVUFRfMA__"><span class="b">MSR_IA32_PACKAGE_THERM_INTERRUPT</span></a>    <span class="c">0x000001b2</span>
<a name="352" /><span class="True">     352:</span> 
<a name="353" /><span class="True">     353:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_UEFDS0FHRV9USEVSTV9JTlRfSElHSF9FTkFCTEVfMA__"><span class="b">PACKAGE_THERM_INT_HIGH_ENABLE</span></a>        <span class="f">(</span><span class="c">1</span> <span class="f">&lt;&lt;</span> <span class="c">0</span><span class="f">)</span>
<a name="354" /><span class="True">     354:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_UEFDS0FHRV9USEVSTV9JTlRfTE9XX0VOQUJMRV8w"><span class="b">PACKAGE_THERM_INT_LOW_ENABLE</span></a>        <span class="f">(</span><span class="c">1</span> <span class="f">&lt;&lt;</span> <span class="c">1</span><span class="f">)</span>
<a name="355" /><span class="True">     355:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_UEFDS0FHRV9USEVSTV9JTlRfUExOX0VOQUJMRV8w"><span class="b">PACKAGE_THERM_INT_PLN_ENABLE</span></a>        <span class="f">(</span><span class="c">1</span> <span class="f">&lt;&lt;</span> <span class="c">24</span><span class="f">)</span>
<a name="356" /><span class="True">     356:</span> 
<a name="357" /><span class="True">     357:</span> <span class="k">/* Thermal Thresholds Support */</span>
<a name="358" /><span class="True">     358:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_VEhFUk1fSU5UX1RIUkVTSE9MRDBfRU5BQkxFXzA_"><span class="b">THERM_INT_THRESHOLD0_ENABLE</span></a>    <span class="f">(</span><span class="c">1</span> <span class="f">&lt;&lt;</span> <span class="c">15</span><span class="f">)</span>
<a name="359" /><span class="True">     359:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_VEhFUk1fU0hJRlRfVEhSRVNIT0xEMF8w"><span class="b">THERM_SHIFT_THRESHOLD0</span></a>        <span class="c">8</span>
<a name="360" /><span class="True">     360:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_VEhFUk1fTUFTS19USFJFU0hPTEQwXzA_"><span class="b">THERM_MASK_THRESHOLD0</span></a>          <span class="f">(</span><span class="c">0x7f</span> <span class="f">&lt;&lt;</span> <a href="cpu.c_macros_noref.html#_VEhFUk1fU0hJRlRfVEhSRVNIT0xEMF8w"><span class="b">THERM_SHIFT_THRESHOLD0</span></a><span class="f">)</span>
<a name="361" /><span class="True">     361:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_VEhFUk1fSU5UX1RIUkVTSE9MRDFfRU5BQkxFXzA_"><span class="b">THERM_INT_THRESHOLD1_ENABLE</span></a>    <span class="f">(</span><span class="c">1</span> <span class="f">&lt;&lt;</span> <span class="c">23</span><span class="f">)</span>
<a name="362" /><span class="True">     362:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_VEhFUk1fU0hJRlRfVEhSRVNIT0xEMV8w"><span class="b">THERM_SHIFT_THRESHOLD1</span></a>        <span class="c">16</span>
<a name="363" /><span class="True">     363:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_VEhFUk1fTUFTS19USFJFU0hPTEQxXzA_"><span class="b">THERM_MASK_THRESHOLD1</span></a>          <span class="f">(</span><span class="c">0x7f</span> <span class="f">&lt;&lt;</span> <a href="cpu.c_macros_noref.html#_VEhFUk1fU0hJRlRfVEhSRVNIT0xEMV8w"><span class="b">THERM_SHIFT_THRESHOLD1</span></a><span class="f">)</span>
<a name="364" /><span class="True">     364:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_VEhFUk1fU1RBVFVTX1RIUkVTSE9MRDBfMA__"><span class="b">THERM_STATUS_THRESHOLD0</span></a>        <span class="f">(</span><span class="c">1</span> <span class="f">&lt;&lt;</span> <span class="c">6</span><span class="f">)</span>
<a name="365" /><span class="True">     365:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_VEhFUk1fTE9HX1RIUkVTSE9MRDBfMA__"><span class="b">THERM_LOG_THRESHOLD0</span></a>           <span class="f">(</span><span class="c">1</span> <span class="f">&lt;&lt;</span> <span class="c">7</span><span class="f">)</span>
<a name="366" /><span class="True">     366:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_VEhFUk1fU1RBVFVTX1RIUkVTSE9MRDFfMA__"><span class="b">THERM_STATUS_THRESHOLD1</span></a>        <span class="f">(</span><span class="c">1</span> <span class="f">&lt;&lt;</span> <span class="c">8</span><span class="f">)</span>
<a name="367" /><span class="True">     367:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_VEhFUk1fTE9HX1RIUkVTSE9MRDFfMA__"><span class="b">THERM_LOG_THRESHOLD1</span></a>           <span class="f">(</span><span class="c">1</span> <span class="f">&lt;&lt;</span> <span class="c">9</span><span class="f">)</span>
<a name="368" /><span class="True">     368:</span> 
<a name="369" /><span class="True">     369:</span> <span class="k">/* MISC_ENABLE bits: architectural */</span>
<a name="370" /><span class="True">     370:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfRkFTVF9TVFJJTkdfMA__"><span class="b">MSR_IA32_MISC_ENABLE_FAST_STRING</span></a>    <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">0</span><span class="f">)</span>
<a name="371" /><span class="True">     371:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfVENDXzA_"><span class="b">MSR_IA32_MISC_ENABLE_TCC</span></a>        <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">1</span><span class="f">)</span>
<a name="372" /><span class="True">     372:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfRU1PTl8w"><span class="b">MSR_IA32_MISC_ENABLE_EMON</span></a>        <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">7</span><span class="f">)</span>
<a name="373" /><span class="True">     373:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfQlRTX1VOQVZBSUxfMA__"><span class="b">MSR_IA32_MISC_ENABLE_BTS_UNAVAIL</span></a>    <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">11</span><span class="f">)</span>
<a name="374" /><span class="True">     374:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfUEVCU19VTkFWQUlMXzA_"><span class="b">MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL</span></a>    <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">12</span><span class="f">)</span>
<a name="375" /><span class="True">     375:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfRU5IQU5DRURfU1BFRURTVEVQXzA_"><span class="b">MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP</span></a>    <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">16</span><span class="f">)</span>
<a name="376" /><span class="True">     376:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfTVdBSVRfMA__"><span class="b">MSR_IA32_MISC_ENABLE_MWAIT</span></a>        <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">18</span><span class="f">)</span>
<a name="377" /><span class="True">     377:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfTElNSVRfQ1BVSURfMA__"><span class="b">MSR_IA32_MISC_ENABLE_LIMIT_CPUID</span></a>    <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">22</span><span class="f">)</span>
<a name="378" /><span class="True">     378:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfWFRQUl9ESVNBQkxFXzA_"><span class="b">MSR_IA32_MISC_ENABLE_XTPR_DISABLE</span></a>    <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">23</span><span class="f">)</span>
<a name="379" /><span class="True">     379:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfWERfRElTQUJMRV8w"><span class="b">MSR_IA32_MISC_ENABLE_XD_DISABLE</span></a>        <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">34</span><span class="f">)</span>
<a name="380" /><span class="True">     380:</span> 
<a name="381" /><span class="True">     381:</span> <span class="k">/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */</span>
<a name="382" /><span class="True">     382:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfWDg3X0NPTVBBVF8w"><span class="b">MSR_IA32_MISC_ENABLE_X87_COMPAT</span></a>        <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">2</span><span class="f">)</span>
<a name="383" /><span class="True">     383:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfVE0xXzA_"><span class="b">MSR_IA32_MISC_ENABLE_TM1</span></a>        <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">3</span><span class="f">)</span>
<a name="384" /><span class="True">     384:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfU1BMSVRfTE9DS19ESVNBQkxFXzA_"><span class="b">MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE</span></a>    <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">4</span><span class="f">)</span>
<a name="385" /><span class="True">     385:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfTDNDQUNIRV9ESVNBQkxFXzA_"><span class="b">MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE</span></a>    <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">6</span><span class="f">)</span>
<a name="386" /><span class="True">     386:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfU1VQUFJFU1NfTE9DS18w"><span class="b">MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK</span></a>    <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">8</span><span class="f">)</span>
<a name="387" /><span class="True">     387:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfUFJFRkVUQ0hfRElTQUJMRV8w"><span class="b">MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE</span></a>    <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">9</span><span class="f">)</span>
<a name="388" /><span class="True">     388:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfRkVSUl8w"><span class="b">MSR_IA32_MISC_ENABLE_FERR</span></a>        <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">10</span><span class="f">)</span>
<a name="389" /><span class="True">     389:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfRkVSUl9NVUxUSVBMRVhfMA__"><span class="b">MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX</span></a>    <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">10</span><span class="f">)</span>
<a name="390" /><span class="True">     390:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfVE0yXzA_"><span class="b">MSR_IA32_MISC_ENABLE_TM2</span></a>        <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">13</span><span class="f">)</span>
<a name="391" /><span class="True">     391:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfQURKX1BSRUZfRElTQUJMRV8w"><span class="b">MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE</span></a>    <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">19</span><span class="f">)</span>
<a name="392" /><span class="True">     392:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfU1BFRURTVEVQX0xPQ0tfMA__"><span class="b">MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK</span></a>    <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">20</span><span class="f">)</span>
<a name="393" /><span class="True">     393:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfTDFEX0NPTlRFWFRfMA__"><span class="b">MSR_IA32_MISC_ENABLE_L1D_CONTEXT</span></a>    <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">24</span><span class="f">)</span>
<a name="394" /><span class="True">     394:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfRENVX1BSRUZfRElTQUJMRV8w"><span class="b">MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE</span></a>    <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">37</span><span class="f">)</span>
<a name="395" /><span class="True">     395:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfVFVSQk9fRElTQUJMRV8w"><span class="b">MSR_IA32_MISC_ENABLE_TURBO_DISABLE</span></a>    <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">38</span><span class="f">)</span>
<a name="396" /><span class="True">     396:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUlTQ19FTkFCTEVfSVBfUFJFRl9ESVNBQkxFXzA_"><span class="b">MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE</span></a>    <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">39</span><span class="f">)</span>
<a name="397" /><span class="True">     397:</span> 
<a name="398" /><span class="True">     398:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVFNDX0RFQURMSU5FXzA_"><span class="b">MSR_IA32_TSC_DEADLINE</span></a>        <span class="c">0x000006E0</span>
<a name="399" /><span class="True">     399:</span> 
<a name="400" /><span class="True">     400:</span> <span class="k">/* P4/Xeon+ specific */</span>
<a name="401" /><span class="True">     401:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUNHX0VBWF8w"><span class="b">MSR_IA32_MCG_EAX</span></a>        <span class="c">0x00000180</span>
<a name="402" /><span class="True">     402:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUNHX0VCWF8w"><span class="b">MSR_IA32_MCG_EBX</span></a>        <span class="c">0x00000181</span>
<a name="403" /><span class="True">     403:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUNHX0VDWF8w"><span class="b">MSR_IA32_MCG_ECX</span></a>        <span class="c">0x00000182</span>
<a name="404" /><span class="True">     404:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUNHX0VEWF8w"><span class="b">MSR_IA32_MCG_EDX</span></a>        <span class="c">0x00000183</span>
<a name="405" /><span class="True">     405:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUNHX0VTSV8w"><span class="b">MSR_IA32_MCG_ESI</span></a>        <span class="c">0x00000184</span>
<a name="406" /><span class="True">     406:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUNHX0VESV8w"><span class="b">MSR_IA32_MCG_EDI</span></a>        <span class="c">0x00000185</span>
<a name="407" /><span class="True">     407:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUNHX0VCUF8w"><span class="b">MSR_IA32_MCG_EBP</span></a>        <span class="c">0x00000186</span>
<a name="408" /><span class="True">     408:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUNHX0VTUF8w"><span class="b">MSR_IA32_MCG_ESP</span></a>        <span class="c">0x00000187</span>
<a name="409" /><span class="True">     409:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUNHX0VGTEFHU18w"><span class="b">MSR_IA32_MCG_EFLAGS</span></a>        <span class="c">0x00000188</span>
<a name="410" /><span class="True">     410:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUNHX0VJUF8w"><span class="b">MSR_IA32_MCG_EIP</span></a>        <span class="c">0x00000189</span>
<a name="411" /><span class="True">     411:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfTUNHX1JFU0VSVkVEXzA_"><span class="b">MSR_IA32_MCG_RESERVED</span></a>        <span class="c">0x0000018a</span>
<a name="412" /><span class="True">     412:</span> 
<a name="413" /><span class="True">     413:</span> <span class="k">/* Pentium IV performance counter MSRs */</span>
<a name="414" /><span class="True">     414:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0JQVV9QRVJGQ1RSMF8w"><span class="b">MSR_P4_BPU_PERFCTR0</span></a>        <span class="c">0x00000300</span>
<a name="415" /><span class="True">     415:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0JQVV9QRVJGQ1RSMV8w"><span class="b">MSR_P4_BPU_PERFCTR1</span></a>        <span class="c">0x00000301</span>
<a name="416" /><span class="True">     416:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0JQVV9QRVJGQ1RSMl8w"><span class="b">MSR_P4_BPU_PERFCTR2</span></a>        <span class="c">0x00000302</span>
<a name="417" /><span class="True">     417:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0JQVV9QRVJGQ1RSM18w"><span class="b">MSR_P4_BPU_PERFCTR3</span></a>        <span class="c">0x00000303</span>
<a name="418" /><span class="True">     418:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X01TX1BFUkZDVFIwXzA_"><span class="b">MSR_P4_MS_PERFCTR0</span></a>        <span class="c">0x00000304</span>
<a name="419" /><span class="True">     419:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X01TX1BFUkZDVFIxXzA_"><span class="b">MSR_P4_MS_PERFCTR1</span></a>        <span class="c">0x00000305</span>
<a name="420" /><span class="True">     420:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X01TX1BFUkZDVFIyXzA_"><span class="b">MSR_P4_MS_PERFCTR2</span></a>        <span class="c">0x00000306</span>
<a name="421" /><span class="True">     421:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X01TX1BFUkZDVFIzXzA_"><span class="b">MSR_P4_MS_PERFCTR3</span></a>        <span class="c">0x00000307</span>
<a name="422" /><span class="True">     422:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0ZMQU1FX1BFUkZDVFIwXzA_"><span class="b">MSR_P4_FLAME_PERFCTR0</span></a>        <span class="c">0x00000308</span>
<a name="423" /><span class="True">     423:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0ZMQU1FX1BFUkZDVFIxXzA_"><span class="b">MSR_P4_FLAME_PERFCTR1</span></a>        <span class="c">0x00000309</span>
<a name="424" /><span class="True">     424:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0ZMQU1FX1BFUkZDVFIyXzA_"><span class="b">MSR_P4_FLAME_PERFCTR2</span></a>        <span class="c">0x0000030a</span>
<a name="425" /><span class="True">     425:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0ZMQU1FX1BFUkZDVFIzXzA_"><span class="b">MSR_P4_FLAME_PERFCTR3</span></a>        <span class="c">0x0000030b</span>
<a name="426" /><span class="True">     426:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0lRX1BFUkZDVFIwXzA_"><span class="b">MSR_P4_IQ_PERFCTR0</span></a>        <span class="c">0x0000030c</span>
<a name="427" /><span class="True">     427:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0lRX1BFUkZDVFIxXzA_"><span class="b">MSR_P4_IQ_PERFCTR1</span></a>        <span class="c">0x0000030d</span>
<a name="428" /><span class="True">     428:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0lRX1BFUkZDVFIyXzA_"><span class="b">MSR_P4_IQ_PERFCTR2</span></a>        <span class="c">0x0000030e</span>
<a name="429" /><span class="True">     429:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0lRX1BFUkZDVFIzXzA_"><span class="b">MSR_P4_IQ_PERFCTR3</span></a>        <span class="c">0x0000030f</span>
<a name="430" /><span class="True">     430:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0lRX1BFUkZDVFI0XzA_"><span class="b">MSR_P4_IQ_PERFCTR4</span></a>        <span class="c">0x00000310</span>
<a name="431" /><span class="True">     431:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0lRX1BFUkZDVFI1XzA_"><span class="b">MSR_P4_IQ_PERFCTR5</span></a>        <span class="c">0x00000311</span>
<a name="432" /><span class="True">     432:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0JQVV9DQ0NSMF8w"><span class="b">MSR_P4_BPU_CCCR0</span></a>        <span class="c">0x00000360</span>
<a name="433" /><span class="True">     433:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0JQVV9DQ0NSMV8w"><span class="b">MSR_P4_BPU_CCCR1</span></a>        <span class="c">0x00000361</span>
<a name="434" /><span class="True">     434:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0JQVV9DQ0NSMl8w"><span class="b">MSR_P4_BPU_CCCR2</span></a>        <span class="c">0x00000362</span>
<a name="435" /><span class="True">     435:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0JQVV9DQ0NSM18w"><span class="b">MSR_P4_BPU_CCCR3</span></a>        <span class="c">0x00000363</span>
<a name="436" /><span class="True">     436:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X01TX0NDQ1IwXzA_"><span class="b">MSR_P4_MS_CCCR0</span></a>            <span class="c">0x00000364</span>
<a name="437" /><span class="True">     437:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X01TX0NDQ1IxXzA_"><span class="b">MSR_P4_MS_CCCR1</span></a>            <span class="c">0x00000365</span>
<a name="438" /><span class="True">     438:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X01TX0NDQ1IyXzA_"><span class="b">MSR_P4_MS_CCCR2</span></a>            <span class="c">0x00000366</span>
<a name="439" /><span class="True">     439:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X01TX0NDQ1IzXzA_"><span class="b">MSR_P4_MS_CCCR3</span></a>            <span class="c">0x00000367</span>
<a name="440" /><span class="True">     440:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0ZMQU1FX0NDQ1IwXzA_"><span class="b">MSR_P4_FLAME_CCCR0</span></a>        <span class="c">0x00000368</span>
<a name="441" /><span class="True">     441:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0ZMQU1FX0NDQ1IxXzA_"><span class="b">MSR_P4_FLAME_CCCR1</span></a>        <span class="c">0x00000369</span>
<a name="442" /><span class="True">     442:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0ZMQU1FX0NDQ1IyXzA_"><span class="b">MSR_P4_FLAME_CCCR2</span></a>        <span class="c">0x0000036a</span>
<a name="443" /><span class="True">     443:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0ZMQU1FX0NDQ1IzXzA_"><span class="b">MSR_P4_FLAME_CCCR3</span></a>        <span class="c">0x0000036b</span>
<a name="444" /><span class="True">     444:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0lRX0NDQ1IwXzA_"><span class="b">MSR_P4_IQ_CCCR0</span></a>            <span class="c">0x0000036c</span>
<a name="445" /><span class="True">     445:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0lRX0NDQ1IxXzA_"><span class="b">MSR_P4_IQ_CCCR1</span></a>            <span class="c">0x0000036d</span>
<a name="446" /><span class="True">     446:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0lRX0NDQ1IyXzA_"><span class="b">MSR_P4_IQ_CCCR2</span></a>            <span class="c">0x0000036e</span>
<a name="447" /><span class="True">     447:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0lRX0NDQ1IzXzA_"><span class="b">MSR_P4_IQ_CCCR3</span></a>            <span class="c">0x0000036f</span>
<a name="448" /><span class="True">     448:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0lRX0NDQ1I0XzA_"><span class="b">MSR_P4_IQ_CCCR4</span></a>            <span class="c">0x00000370</span>
<a name="449" /><span class="True">     449:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0lRX0NDQ1I1XzA_"><span class="b">MSR_P4_IQ_CCCR5</span></a>            <span class="c">0x00000371</span>
<a name="450" /><span class="True">     450:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0FMRl9FU0NSMF8w"><span class="b">MSR_P4_ALF_ESCR0</span></a>        <span class="c">0x000003ca</span>
<a name="451" /><span class="True">     451:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0FMRl9FU0NSMV8w"><span class="b">MSR_P4_ALF_ESCR1</span></a>        <span class="c">0x000003cb</span>
<a name="452" /><span class="True">     452:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0JQVV9FU0NSMF8w"><span class="b">MSR_P4_BPU_ESCR0</span></a>        <span class="c">0x000003b2</span>
<a name="453" /><span class="True">     453:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0JQVV9FU0NSMV8w"><span class="b">MSR_P4_BPU_ESCR1</span></a>        <span class="c">0x000003b3</span>
<a name="454" /><span class="True">     454:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0JTVV9FU0NSMF8w"><span class="b">MSR_P4_BSU_ESCR0</span></a>        <span class="c">0x000003a0</span>
<a name="455" /><span class="True">     455:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0JTVV9FU0NSMV8w"><span class="b">MSR_P4_BSU_ESCR1</span></a>        <span class="c">0x000003a1</span>
<a name="456" /><span class="True">     456:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0NSVV9FU0NSMF8w"><span class="b">MSR_P4_CRU_ESCR0</span></a>        <span class="c">0x000003b8</span>
<a name="457" /><span class="True">     457:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0NSVV9FU0NSMV8w"><span class="b">MSR_P4_CRU_ESCR1</span></a>        <span class="c">0x000003b9</span>
<a name="458" /><span class="True">     458:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0NSVV9FU0NSMl8w"><span class="b">MSR_P4_CRU_ESCR2</span></a>        <span class="c">0x000003cc</span>
<a name="459" /><span class="True">     459:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0NSVV9FU0NSM18w"><span class="b">MSR_P4_CRU_ESCR3</span></a>        <span class="c">0x000003cd</span>
<a name="460" /><span class="True">     460:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0NSVV9FU0NSNF8w"><span class="b">MSR_P4_CRU_ESCR4</span></a>        <span class="c">0x000003e0</span>
<a name="461" /><span class="True">     461:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0NSVV9FU0NSNV8w"><span class="b">MSR_P4_CRU_ESCR5</span></a>        <span class="c">0x000003e1</span>
<a name="462" /><span class="True">     462:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0RBQ19FU0NSMF8w"><span class="b">MSR_P4_DAC_ESCR0</span></a>        <span class="c">0x000003a8</span>
<a name="463" /><span class="True">     463:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0RBQ19FU0NSMV8w"><span class="b">MSR_P4_DAC_ESCR1</span></a>        <span class="c">0x000003a9</span>
<a name="464" /><span class="True">     464:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0ZJUk1fRVNDUjBfMA__"><span class="b">MSR_P4_FIRM_ESCR0</span></a>        <span class="c">0x000003a4</span>
<a name="465" /><span class="True">     465:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0ZJUk1fRVNDUjFfMA__"><span class="b">MSR_P4_FIRM_ESCR1</span></a>        <span class="c">0x000003a5</span>
<a name="466" /><span class="True">     466:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0ZMQU1FX0VTQ1IwXzA_"><span class="b">MSR_P4_FLAME_ESCR0</span></a>        <span class="c">0x000003a6</span>
<a name="467" /><span class="True">     467:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0ZMQU1FX0VTQ1IxXzA_"><span class="b">MSR_P4_FLAME_ESCR1</span></a>        <span class="c">0x000003a7</span>
<a name="468" /><span class="True">     468:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0ZTQl9FU0NSMF8w"><span class="b">MSR_P4_FSB_ESCR0</span></a>        <span class="c">0x000003a2</span>
<a name="469" /><span class="True">     469:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0ZTQl9FU0NSMV8w"><span class="b">MSR_P4_FSB_ESCR1</span></a>        <span class="c">0x000003a3</span>
<a name="470" /><span class="True">     470:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0lRX0VTQ1IwXzA_"><span class="b">MSR_P4_IQ_ESCR0</span></a>            <span class="c">0x000003ba</span>
<a name="471" /><span class="True">     471:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0lRX0VTQ1IxXzA_"><span class="b">MSR_P4_IQ_ESCR1</span></a>            <span class="c">0x000003bb</span>
<a name="472" /><span class="True">     472:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0lTX0VTQ1IwXzA_"><span class="b">MSR_P4_IS_ESCR0</span></a>            <span class="c">0x000003b4</span>
<a name="473" /><span class="True">     473:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0lTX0VTQ1IxXzA_"><span class="b">MSR_P4_IS_ESCR1</span></a>            <span class="c">0x000003b5</span>
<a name="474" /><span class="True">     474:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0lUTEJfRVNDUjBfMA__"><span class="b">MSR_P4_ITLB_ESCR0</span></a>        <span class="c">0x000003b6</span>
<a name="475" /><span class="True">     475:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0lUTEJfRVNDUjFfMA__"><span class="b">MSR_P4_ITLB_ESCR1</span></a>        <span class="c">0x000003b7</span>
<a name="476" /><span class="True">     476:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0lYX0VTQ1IwXzA_"><span class="b">MSR_P4_IX_ESCR0</span></a>            <span class="c">0x000003c8</span>
<a name="477" /><span class="True">     477:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X0lYX0VTQ1IxXzA_"><span class="b">MSR_P4_IX_ESCR1</span></a>            <span class="c">0x000003c9</span>
<a name="478" /><span class="True">     478:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X01PQl9FU0NSMF8w"><span class="b">MSR_P4_MOB_ESCR0</span></a>        <span class="c">0x000003aa</span>
<a name="479" /><span class="True">     479:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X01PQl9FU0NSMV8w"><span class="b">MSR_P4_MOB_ESCR1</span></a>        <span class="c">0x000003ab</span>
<a name="480" /><span class="True">     480:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X01TX0VTQ1IwXzA_"><span class="b">MSR_P4_MS_ESCR0</span></a>            <span class="c">0x000003c0</span>
<a name="481" /><span class="True">     481:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X01TX0VTQ1IxXzA_"><span class="b">MSR_P4_MS_ESCR1</span></a>            <span class="c">0x000003c1</span>
<a name="482" /><span class="True">     482:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X1BNSF9FU0NSMF8w"><span class="b">MSR_P4_PMH_ESCR0</span></a>        <span class="c">0x000003ac</span>
<a name="483" /><span class="True">     483:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X1BNSF9FU0NSMV8w"><span class="b">MSR_P4_PMH_ESCR1</span></a>        <span class="c">0x000003ad</span>
<a name="484" /><span class="True">     484:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X1JBVF9FU0NSMF8w"><span class="b">MSR_P4_RAT_ESCR0</span></a>        <span class="c">0x000003bc</span>
<a name="485" /><span class="True">     485:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X1JBVF9FU0NSMV8w"><span class="b">MSR_P4_RAT_ESCR1</span></a>        <span class="c">0x000003bd</span>
<a name="486" /><span class="True">     486:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X1NBQVRfRVNDUjBfMA__"><span class="b">MSR_P4_SAAT_ESCR0</span></a>        <span class="c">0x000003ae</span>
<a name="487" /><span class="True">     487:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X1NBQVRfRVNDUjFfMA__"><span class="b">MSR_P4_SAAT_ESCR1</span></a>        <span class="c">0x000003af</span>
<a name="488" /><span class="True">     488:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X1NTVV9FU0NSMF8w"><span class="b">MSR_P4_SSU_ESCR0</span></a>        <span class="c">0x000003be</span>
<a name="489" /><span class="True">     489:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X1NTVV9FU0NSMV8w"><span class="b">MSR_P4_SSU_ESCR1</span></a>        <span class="c">0x000003bf</span> <span class="k">/* guess: not in manual */</span>
<a name="490" /><span class="True">     490:</span> 
<a name="491" /><span class="True">     491:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X1RCUFVfRVNDUjBfMA__"><span class="b">MSR_P4_TBPU_ESCR0</span></a>        <span class="c">0x000003c2</span>
<a name="492" /><span class="True">     492:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X1RCUFVfRVNDUjFfMA__"><span class="b">MSR_P4_TBPU_ESCR1</span></a>        <span class="c">0x000003c3</span>
<a name="493" /><span class="True">     493:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X1RDX0VTQ1IwXzA_"><span class="b">MSR_P4_TC_ESCR0</span></a>            <span class="c">0x000003c4</span>
<a name="494" /><span class="True">     494:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X1RDX0VTQ1IxXzA_"><span class="b">MSR_P4_TC_ESCR1</span></a>            <span class="c">0x000003c5</span>
<a name="495" /><span class="True">     495:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X1UyTF9FU0NSMF8w"><span class="b">MSR_P4_U2L_ESCR0</span></a>        <span class="c">0x000003b0</span>
<a name="496" /><span class="True">     496:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X1UyTF9FU0NSMV8w"><span class="b">MSR_P4_U2L_ESCR1</span></a>        <span class="c">0x000003b1</span>
<a name="497" /><span class="True">     497:</span> 
<a name="498" /><span class="True">     498:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1A0X1BFQlNfTUFUUklYX1ZFUlRfMA__"><span class="b">MSR_P4_PEBS_MATRIX_VERT</span></a>        <span class="c">0x000003f2</span>
<a name="499" /><span class="True">     499:</span> 
<a name="500" /><span class="True">     500:</span> <span class="k">/* Intel Core-based CPU performance counters */</span>
<a name="501" /><span class="True">     501:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0NPUkVfUEVSRl9GSVhFRF9DVFIwXzA_"><span class="b">MSR_CORE_PERF_FIXED_CTR0</span></a>    <span class="c">0x00000309</span>
<a name="502" /><span class="True">     502:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0NPUkVfUEVSRl9GSVhFRF9DVFIxXzA_"><span class="b">MSR_CORE_PERF_FIXED_CTR1</span></a>    <span class="c">0x0000030a</span>
<a name="503" /><span class="True">     503:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0NPUkVfUEVSRl9GSVhFRF9DVFIyXzA_"><span class="b">MSR_CORE_PERF_FIXED_CTR2</span></a>    <span class="c">0x0000030b</span>
<a name="504" /><span class="True">     504:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0NPUkVfUEVSRl9GSVhFRF9DVFJfQ1RSTF8w"><span class="b">MSR_CORE_PERF_FIXED_CTR_CTRL</span></a>    <span class="c">0x0000038d</span>
<a name="505" /><span class="True">     505:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0NPUkVfUEVSRl9HTE9CQUxfU1RBVFVTXzA_"><span class="b">MSR_CORE_PERF_GLOBAL_STATUS</span></a>    <span class="c">0x0000038e</span>
<a name="506" /><span class="True">     506:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0NPUkVfUEVSRl9HTE9CQUxfQ1RSTF8w"><span class="b">MSR_CORE_PERF_GLOBAL_CTRL</span></a>    <span class="c">0x0000038f</span>
<a name="507" /><span class="True">     507:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0NPUkVfUEVSRl9HTE9CQUxfT1ZGX0NUUkxfMA__"><span class="b">MSR_CORE_PERF_GLOBAL_OVF_CTRL</span></a>    <span class="c">0x00000390</span>
<a name="508" /><span class="True">     508:</span> 
<a name="509" /><span class="True">     509:</span> <span class="k">/* Geode defined MSRs */</span>
<a name="510" /><span class="True">     510:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0dFT0RFX0JVU0NPTlRfQ09ORjBfMA__"><span class="b">MSR_GEODE_BUSCONT_CONF0</span></a>        <span class="c">0x00001900</span>
<a name="511" /><span class="True">     511:</span> 
<a name="512" /><span class="True">     512:</span> <span class="k">/* Intel VT MSRs */</span>
<a name="513" /><span class="True">     513:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVk1YX0JBU0lDXzA_"><span class="b">MSR_IA32_VMX_BASIC</span></a>              <span class="c">0x00000480</span>
<a name="514" /><span class="True">     514:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVk1YX1BJTkJBU0VEX0NUTFNfMA__"><span class="b">MSR_IA32_VMX_PINBASED_CTLS</span></a>      <span class="c">0x00000481</span>
<a name="515" /><span class="True">     515:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVk1YX1BST0NCQVNFRF9DVExTXzA_"><span class="b">MSR_IA32_VMX_PROCBASED_CTLS</span></a>     <span class="c">0x00000482</span>
<a name="516" /><span class="True">     516:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVk1YX0VYSVRfQ1RMU18w"><span class="b">MSR_IA32_VMX_EXIT_CTLS</span></a>          <span class="c">0x00000483</span>
<a name="517" /><span class="True">     517:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVk1YX0VOVFJZX0NUTFNfMA__"><span class="b">MSR_IA32_VMX_ENTRY_CTLS</span></a>         <span class="c">0x00000484</span>
<a name="518" /><span class="True">     518:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVk1YX01JU0NfMA__"><span class="b">MSR_IA32_VMX_MISC</span></a>               <span class="c">0x00000485</span>
<a name="519" /><span class="True">     519:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVk1YX0NSMF9GSVhFRDBfMA__"><span class="b">MSR_IA32_VMX_CR0_FIXED0</span></a>         <span class="c">0x00000486</span>
<a name="520" /><span class="True">     520:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVk1YX0NSMF9GSVhFRDFfMA__"><span class="b">MSR_IA32_VMX_CR0_FIXED1</span></a>         <span class="c">0x00000487</span>
<a name="521" /><span class="True">     521:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVk1YX0NSNF9GSVhFRDBfMA__"><span class="b">MSR_IA32_VMX_CR4_FIXED0</span></a>         <span class="c">0x00000488</span>
<a name="522" /><span class="True">     522:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVk1YX0NSNF9GSVhFRDFfMA__"><span class="b">MSR_IA32_VMX_CR4_FIXED1</span></a>         <span class="c">0x00000489</span>
<a name="523" /><span class="True">     523:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVk1YX1ZNQ1NfRU5VTV8w"><span class="b">MSR_IA32_VMX_VMCS_ENUM</span></a>          <span class="c">0x0000048a</span>
<a name="524" /><span class="True">     524:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVk1YX1BST0NCQVNFRF9DVExTMl8w"><span class="b">MSR_IA32_VMX_PROCBASED_CTLS2</span></a>    <span class="c">0x0000048b</span>
<a name="525" /><span class="True">     525:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVk1YX0VQVF9WUElEX0NBUF8w"><span class="b">MSR_IA32_VMX_EPT_VPID_CAP</span></a>       <span class="c">0x0000048c</span>
<a name="526" /><span class="True">     526:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVk1YX1RSVUVfUElOQkFTRURfQ1RMU18w"><span class="b">MSR_IA32_VMX_TRUE_PINBASED_CTLS</span></a>  <span class="c">0x0000048d</span>
<a name="527" /><span class="True">     527:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVk1YX1RSVUVfUFJPQ0JBU0VEX0NUTFNfMA__"><span class="b">MSR_IA32_VMX_TRUE_PROCBASED_CTLS</span></a> <span class="c">0x0000048e</span>
<a name="528" /><span class="True">     528:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVk1YX1RSVUVfRVhJVF9DVExTXzA_"><span class="b">MSR_IA32_VMX_TRUE_EXIT_CTLS</span></a>      <span class="c">0x0000048f</span>
<a name="529" /><span class="True">     529:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVk1YX1RSVUVfRU5UUllfQ1RMU18w"><span class="b">MSR_IA32_VMX_TRUE_ENTRY_CTLS</span></a>     <span class="c">0x00000490</span>
<a name="530" /><span class="True">     530:</span> 
<a name="531" /><span class="True">     531:</span> <span class="k">/* VMX_BASIC bits and bitmasks */</span>
<a name="532" /><span class="True">     532:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Vk1YX0JBU0lDX1ZNQ1NfU0laRV9TSElGVF8w"><span class="b">VMX_BASIC_VMCS_SIZE_SHIFT</span></a>    <span class="c">32</span>
<a name="533" /><span class="True">     533:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Vk1YX0JBU0lDXzY0XzA_"><span class="b">VMX_BASIC_64</span></a>        <span class="c">0x0001000000000000LLU</span>
<a name="534" /><span class="True">     534:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Vk1YX0JBU0lDX01FTV9UWVBFX1NISUZUXzA_"><span class="b">VMX_BASIC_MEM_TYPE_SHIFT</span></a>    <span class="c">50</span>
<a name="535" /><span class="True">     535:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Vk1YX0JBU0lDX01FTV9UWVBFX01BU0tfMA__"><span class="b">VMX_BASIC_MEM_TYPE_MASK</span></a>    <span class="c">0x003c000000000000LLU</span>
<a name="536" /><span class="True">     536:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Vk1YX0JBU0lDX01FTV9UWVBFX1dCXzA_"><span class="b">VMX_BASIC_MEM_TYPE_WB</span></a>    <span class="c">6LLU</span>
<a name="537" /><span class="True">     537:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Vk1YX0JBU0lDX0lOT1VUXzA_"><span class="b">VMX_BASIC_INOUT</span></a>        <span class="c">0x0040000000000000LLU</span>
<a name="538" /><span class="True">     538:</span> 
<a name="539" /><span class="True">     539:</span> <span class="k">/* MSR_IA32_VMX_MISC bits */</span>
<a name="540" /><span class="True">     540:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVk1YX01JU0NfVk1XUklURV9TSEFET1dfUk9fRklFTERTXzA_"><span class="b">MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS</span></a> <span class="f">(</span><span class="c">1ULL</span> <span class="f">&lt;&lt;</span> <span class="c">29</span><span class="f">)</span>
<a name="541" /><span class="True">     541:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX0lBMzJfVk1YX01JU0NfUFJFRU1QVElPTl9USU1FUl9TQ0FMRV8w"><span class="b">MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE</span></a>   <span class="c">0x1F</span>
<a name="542" /><span class="True">     542:</span> <span class="k">/* AMD-V MSRs */</span>
<a name="543" /><span class="True">     543:</span> 
<a name="544" /><span class="True">     544:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1ZNX0NSXzA_"><span class="b">MSR_VM_CR</span></a>                       <span class="c">0xc0010114</span>
<a name="545" /><span class="True">     545:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1ZNX0lHTk5FXzA_"><span class="b">MSR_VM_IGNNE</span></a>                    <span class="c">0xc0010115</span>
<a name="546" /><span class="True">     546:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TVNSX1ZNX0hTQVZFX1BBXzA_"><span class="b">MSR_VM_HSAVE_PA</span></a>                 <span class="c">0xc0010117</span>
<a name="547" /><span class="True">     547:</span> 
<a name="548" /><span class="True">     548:</span> <span class="f">#</span><span class="n">endif</span> <span class="k">/* _ASM_X86_MSR_INDEX_H */</span>
<a name="549" /><span class="True">     549:</span> </pre>
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